SNVSC75B April   2023  – September 2025 LM5171-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Bias Supplies and Voltage Reference (VCC, VDD, and VREF)
      2. 6.3.2  Undervoltage Lockout (UVLO)
      3. 6.3.3  Device Configurations (CFG)
      4. 6.3.4  High Voltage Inputs (HV1, HV2)
      5. 6.3.5  Current Sense Amplifier
      6. 6.3.6  Control Commands
        1. 6.3.6.1 Channel Enable Commands (EN1, EN2)
        2. 6.3.6.2 Direction Command (DIR1 and DIR2)
        3. 6.3.6.3 Channel Current Setting Commands (ISET1 and ISET2)
      7. 6.3.7  Channel Current Monitor (IMON1, IMON2)
        1. 6.3.7.1 Individual Channel Current Monitor
        2. 6.3.7.2 Multiphase Total Current Monitoring
      8. 6.3.8  Cycle-by-Cycle Peak Current Limit (IPK)
      9. 6.3.9  Inner Current Loop Error Amplifier
      10. 6.3.10 Outer Voltage Loop Error Amplifier
      11. 6.3.11 Soft Start, Diode Emulation, and Forced PWM Control (SS/DEM1 and SS/DEM2)
        1. 6.3.11.1 ISET Soft-Start Control by the SS/DEM Pins
        2. 6.3.11.2 DEM Programming
        3. 6.3.11.3 FPWM Programming and Dynamic FPWM and DEM Change
      12. 6.3.12 Gate Drive Outputs, Dead Time Programming and Adaptive Dead Time (HO1, HO2, LO1, LO2, DT/SD)
      13. 6.3.13 Emergency Latched Shutdown (DT/SD)
      14. 6.3.14 PWM Comparator
      15. 6.3.15 Oscillator (OSC)
      16. 6.3.16 Synchronization to an External Clock (SYNCI, SYNCO)
      17. 6.3.17 Overvoltage Protection (OVP)
      18. 6.3.18 Multiphase Configurations (SYNCO, OPT)
        1. 6.3.18.1 Multiphase in Star Configuration
        2. 6.3.18.2 Daisy-Chain Configurations for 2, 3, or 4 Phases parallel operations
        3. 6.3.18.3 Daisy-Chain configuration for 6 or 8 phases parallel operation
      19. 6.3.19 Thermal Shutdown
    4. 6.4 Device Functional Modes
      1. 6.4.1 Initialization Mode
      2. 6.4.2 Standby Mode
      3. 6.4.3 Power Delivery Mode
      4. 6.4.4 Shutdown Mode
      5. 6.4.5 Latched Shutdown mode
  8. 7 Registers
    1. 7.1 I2C Serial Interface
    2. 7.2 I2C Bus Operation
    3. 7.3 Clock Stretching
    4. 7.4 Data Transfer Formats
    5. 7.5 Single READ From a Defined Register Address
    6. 7.6 Sequential READ Starting From a Defined Register Address
    7. 7.7 Single WRITE to a Defined Register Address
    8. 7.8 Sequential WRITE Starting From A Defined Register Address
    9. 7.9 REGFIELD Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Small Signal Model
        1. 8.1.1.1 Current Loop Small Signal Model
        2. 8.1.1.2 Current Loop Compensation
        3. 8.1.1.3 Voltage Loop Small Signal Model
        4. 8.1.1.4 Voltage Loop Compensation
    2. 8.2 PWM to ISET Pins
    3. 8.3 ISET Clamp
    4. 8.4 Dynamic Dead Time Adjustment
    5. 8.5 Proper Termination of Unused Pins
    6. 8.6 Typical Application
      1. 8.6.1 60A, Dual-Phase, 48V to 12V Bidirectional Converter
        1. 8.6.1.1 Design Requirements
        2. 8.6.1.2 Detailed Design Procedure
          1. 8.6.1.2.1  Determining the Duty Cycle
          2. 8.6.1.2.2  Oscillator Programming (OSC)
          3. 8.6.1.2.3  Power Inductor, RMS and Peak Currents
          4. 8.6.1.2.4  Current Sense (RCS)
          5. 8.6.1.2.5  Current Setting Commands (ISETx)
          6. 8.6.1.2.6  Peak Current Limit (IPK)
          7. 8.6.1.2.7  Power MOSFETS
          8. 8.6.1.2.8  Bias Supply
          9. 8.6.1.2.9  Boot Strap Capacitor
          10. 8.6.1.2.10 Overvoltage Protection (OVP)
          11. 8.6.1.2.11 Dead Time (DT/SD)
          12. 8.6.1.2.12 Channel Current Monitor (IMONx)
          13. 8.6.1.2.13 Undervoltage Lockout (UVLO)
          14. 8.6.1.2.14 HVx Pin Configuration
          15. 8.6.1.2.15 Loop Compensation
          16. 8.6.1.2.16 Soft Start (SS/DEMx)
        3. 8.6.1.3 Application Curves
          1. 8.6.1.3.1 Efficiency and Thermal Performance
          2. 8.6.1.3.2 Step Load Response
          3. 8.6.1.3.3 Dual-Channel Interleaving Operation
          4. 8.6.1.3.4 Typical Start Up and Shutdown
          5. 8.6.1.3.5 DEM and FPWM
          6. 8.6.1.3.6 Mode Transition Between DEM and FPWM
          7. 8.6.1.3.7 ISET Tracking and Pre-charge
          8. 8.6.1.3.8 Protections
    7. 8.7 Power Supply Recommendations
    8. 8.8 Layout
      1. 8.8.1 Layout Guidelines
      2. 8.8.2 Layout Examples
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

5.5 Electrical Characteristics

Typical values correspond to TJ = 25°C. Minimum and maximum limits apply over TJ = –40°C to 150°C. Unless otherwise stated, FOSC = 100 kHz; VVCC = 10 V; VHV1 = VHV2 = VHV-Port = 48V and VLV-Port = 12 V.
SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
HV Port (HV1, HV2)
ISHUTDOWN1 HV1 pin current in shutdown mode VUVLO = 0V 10 µA
ISHUTDOWN2 HV2 pin current in shutdown mode VUVLO = 0V 10 µA
IOPERATING HV1 and HV2 pin current in operating VUVLO > 2.6V, VVCC > 9V 1 mA
VCC Bias Supply (VCC)
VVCC_reg VCC LDO regulation setting point VHV1 > 10V 8.55 9 9.45 V
VCCUVLO VCC undervoltage detection VCC falling 7.7 8 8.2 V
VCCHYS VCC UVLO hysteresis VCC rising 8.2 8.5 8.7 V
IVCC_SD VCC sink current in shutdown mode VUVLO = 0V, VVCC=10V 25 µA
IVCC_SB VCC sink current in standby: no switching VUVLO > 2.6V, VVCC > 9V, EN1=EN2=0V 10 mA
VDD Analog Bias Supply (VDD)
VVDD VDD voltage VUVLO > 2.6V, VVCC > 9V 4.75 5 5.25 V
VDDUV VDD undervoltage detection VDD falling 4.25 4.5 4.75 V
VDDHYS VDD UVLO hysteresis VDD rising above VDDUV 0.1 0.2 0.3 V
IVDD VDD source current limit VVDD = 4.6V 10 mA
VOLTAGE REFERENCE (VREF)
VREF Voltage reference VUVLO > 2.6V, VVCC > 9V, VVDD > VDDUV 3.465 3.500 3.535 V
IVREF VREF source current limit VVREF = 3.5V 2 mA
Primary ON/OFF Control (UVLO)
VUVLO_TH UVLO release threshold UVLO voltage rising 2.4 2.5 2.6 V
IHYS UVLO hysteresis current UVLO source current when VUVLO > 2.6V 21 25 29 µA
VRES UVLO shutdown and IC reset voltage threshold UVLO voltage falling 1 1.25 1.5 V
UVLO shutdown release  UVLO voltage rising above VRES 0.15 0.25 0.35 V
tUVLO UVLO 2.5V threshold glitch filter UVLO voltage both rising and falling 2.5 µs
tVRES UVLO 1.25V VRES threshold glitch filter  5 10 µs
UVLO internal pull-down current 25 100 250 nA
Enable Inputs EN1 and EN2
VIL Enable input low state The driver outputs disabled 1.0 V
VIH Enable input high state The driver outputs enabled 2.0 V
Internal pulldown impedance EN1, EN2 logic inputs internal pulldown resistor 0.7 1 1.3 MegΩ
EN glitch filter time (the rising and falling edges) 2.5 µs
DIRECTION COMMANDS (DIR1, DIR2)
VDIR1, VDIR2 Command for current flowing from LV-Port to HV-Port (boost mode 12 V to 48 V), for CH-1 and CH-2, respectively Actively pulled low by external circuit 1 V
VDIR1, VDIR2 Command for current flowing from HV-Port to LV-Port (buck mode 48 V to 12 V), for CH-1 and CH-2, respectively Actively pulled high by external circuit 2 V
VDIR1, VDIR2 Standby (invalid DIR command) DIR pin (DIR1 or DIR2) neither active High nor active Low 1.5 V
DIR glitch filter (the rising and falling edges) Both Rising and Falling Edges 10 µs
ISET INPUTS (ISET1, ISET2)
ISET DC Offset Voltage 0.87 1.0 1.13 V
GISET Gain of the regulated inductor DC current sense voltage to ISET voltage |VCSA – VCSB| = 50mV 24.3 25 25.7 mV/V
ISET internal pull-down current sink 75 200 nA
Output Current Monitor (IMON1, IMON2)
Gain of IMON1 and IMON2 current source versus channel current sense voltage |CSA-CSB| = 50mV,  CONFIG = 'IMON_IL monitor", VDIR > 2V 1.96 2 2.04 µA/mV
Gain of IMON1 and IMON2 current source versus channel current sense voltage |CSA-CSB| = 50mV,  CONFIG = 'IMON_IL monitor",  VDIR < 1V 1.96 2 2.04 uA/mV
Gain of IMON1 and IMON2 current source versus channel current sense voltage |CSA-CSB| = 50mV,  CONFIG = 'IMON_BSTOUT monitor", VDIR < 1V, Duty cycle = 0.75 0.475 0.5 0.525 uA/mV
Gain of IMON1 and IMON2 current source versus channel current sense voltage |CSA-CSB| = 10mV,  CONFIG = "IMON_IL monitor", VDIR > 2V 1.96 2 2.04 uA/mV
Gain of IMON1 and IMON2 current source versus channel current sense voltage |CSA-CSB| = 10mV,  CONFIG = 'IMON_IL monitor",  VDIR < 1V 1.96 2 2.04 uA/mV
Gain of IMON1 and IMON2 current source versus channel current sense voltage |CSA-CSB| = 10mV,  CONFIG = 'IMON_BSTOUT monitor", VDIR < 1V, Duty cycle = 0.75 0.475 0.5 0.525 uA/mV
IMON1 and IMON2 DC offset current |CSA-CSB| = 0mV 42 50 56 µA
CURRENT SENSE AMPLIFIER (BOTH CHANNELS)
GCS_BK1 Gain of amplifier output to current sense voltage in buck mode |VCSA – VCSB| = 50mV, VDIR > 2V 39 40 41 V/V
GCS_BST1 Gain of  amplifier output to current sense voltage in boost mode |VCSA – VCSB| = 50mV, VDIR < 1V 39 40 41 V/V
GCS_BK2 Gain of amplifier output to current sense voltage in buck mode |VCSA – VCSB| = 10mV, VDIR > 2V 38.4 40 41.7 V/V
GCS_BST2 Gain of amplifier output to current sense voltage in boost mode |VCSA – VCSB| = 10mV, VDIR < 1V 38.4 40 41.7 V/V
TRANSCONDUCTION AMPLIFIER (COMP1, COMP2)
Gm Transconductance 75 100 125 µA/V
ICOMP Output source current limit VISET = 4V, |VCSA – VCSB| = 0mV 190 250 280 µA
Output sink current limit VISET = 0V, VCSA – VCSB = 50mV in the buck mode, or VCSA – VCSB = -50mV in the boost mode –280 –250 –190 µA
VOLTAGE LOOP ERROR AMPLIFIERS (VSET, LVFB, LVERR, HVFB, HVERR)
AOL Open loop gain VVCC > 9 V, VVDD > VDDUV 80 dB
FBW Unity gain bandwidth 2.1 MHz
VOS Input offset voltage 0 5 mV
VERR_MIN Minimum amplifier output voltage Sourcing 2mA 4 V
VERR_MAX Maximum amplifier output voltage Sinking 2mA 0.5 V
PWM Comparator
COMP to output delay 50 ns
COMP to PWM comparator offset 1 V
TOFF_MIN Minimum off time 100 150 ns
PEAK CURRENT LIMIT (IPK)
GIPK_BK1 Gain from current sense voltage to cycle-by-cycle limit threshold voltage given at IPK pin, in buck mode VIPK = 3V, VDIR >2V 45 50 55 mV/V
GIPK_BK2 Gain from current sense voltage to cycle-by-cycle limit threshold voltage given at IPK pin, in buck mode VIPK = 1V, VDIR >2V 45 50 55 mV/V
GIPK_BST1 Gain from current sense voltage to cycle-by-cycle limit threshold voltage given at IPK pin, in boost mode VIPK = 3V, VDIR <1V 45 50 55 mV/V
GIPK_BST2 Gain from current sense voltage to cycle-by-cycle limit threshold voltage given at IPK pin, in boost mode VIPK = 1V, VDIR <1V 45 50 55 mV/V
OVERVOLTAGE PROTECTION (OVP)
OVP threshold 0.99 1 1.01 V
OVPHYS OVP Hysteresis 100 mV
tOVP OVP Glitch Filter 5 us
OSCILLATOR (OSC)
FOSC Oscillator frequency 1 ROSC = 41.5kΩ, no external clock signal at SYNCI pin 90 100 110 kHz
Oscillator frequency 2 ROSC = 4.15kΩ,  no external clock signal at SYNCI pin 900 1000 1100 kHz
VOSC OSC pin DC voltage OSC DC Level 1 V
SYNCHRONIZATION CLOCK INPUT (SYNCI)
VSYNIH SYNCI input threshold for high state 2 V
VSYNIL SYNCI input threshold for low state 1 V
Delay to establish synchronization 0.8 x FOSC < FSYNCI < 1.2 x Fosc 200 300 us
Internal pull-down impedance VSYNCI = 2.5V 700 1000 1300 kΩ
SYNCHRONIZATION CLOCK OUTPUT (SYNCO)
VSYNOH SYNCO high state 2.5 V
VSYNOL SYNCO low state 0.4 V
Sourcing current when SYNCO in high state VSYNCO = 2.5V 1 mA
Sinking current when SYNCO in low state VSYNCO = 0.5V 1 mA
SYNCO pulse width 60 90 120 ns
SYNCO pulse delay for multiphase daisy chain connection VOPT > 2V, RSYNCO > 61.9kΩ 90 Degree
VOPT < 1V, RSYNCO > 61.9kΩ 120 Degree
BOOTSTRAP (HB1, HB2)
VHB-UV Bootstrap undervoltage threshold (VHB – VSW) voltage rising 6 6.5 7 V
VHB-UV-HYS Bootstrap undervoltage hysteresis 0.5 V
IHB_LK Bootstrap quiescent current VHB – VSW = 10V, VHO – VSW = 0V 100 µA
HIGH SIDE GATE DRIVERS (HO1, HO2)
VOLH HO low-state output voltage IHO = 100mA 0.1 V
VOHH HO high-state output voltage IHO = -100mA, VOHH = VHB - VHO 0.15 V
HO rise time (10% to 90% pulse magnitude) CLD = 1000pF 5 ns
HO fall time (90% to 10% pulse magnitude CLD = 1000pF 4 ns
IOHH HO peak source current VHB – VSW = 10V 4 A
IOLH HO peak sink current VHB – VSW = 10V 5 A
LOW SIDE GATE DRIVERS (LO1, LO2)
VOLL LO low-state output voltage ILO = 100mA 0.1 V
VOHL LO high-state output voltage ILO = -100mA, VOHL = VVCC - VLO 0.15 V
LO rise time (10% to 90% pulse magnitude) CLD = 1000pF 5 ns
LO fall time (90% to 10% pulse magnitude) CLD = 1000pF 4 ns
IOHL LO peak source current VVCC = 10V 4 A
IOLL LO peak sink current VVCC = 10V 5 A
INTERLEAVE PHASE DELAY FROM CH-2 To CH-1 (OPT)
VOPTL OPT Input Low State OPT="0" 1.0 V
VOPTH OPT Input High State OPT="1" 2.0 V
HO2rising -HO1rising in the buck mode, or LO2rising -LO1rising in the boost mode OPT = "0" for 3 Phases in Daisy Chain Interleaving Operation 240 Degree
HO2rising -HO1rising in the buck mode, or LO2rising -LO1rising in the boost mode OPT= "1" for 1, 2, or 4 phases in Daisy Chain Interleaving Operation 180 Degree
Internal Pull down impedance 1 MegΩ
DEAD TIME and LATCHED SHUTDOWN (DT/SD)
tDT LO falling edge to HO rising edge delay RDT = 19.1kΩ 35 50 60 ns
HO falling edge to LO rising edge delay RDT = 19.1kΩ 35 50 65 ns
VDT DC voltage level for dead time programming 1.2 V
DC voltage level for adaptive dead time programming 3.1 V
VADPT HO-SW or LO-GND voltage threshold to enable cross output for adaptive dead time scheme VVCC > 9V, (VHB – VSW) > 8V, HO or LO voltage falling 1.5 V
tADPT LO falling edge to HO rising edge delay VDT = VVDD 28 40 75 ns
HO falling edge to LO rising edge delay VDT = VVDD 30 40 75 ns
tSD Latched shutdown glitch filter 1.875 2.5 3.125 µs
RSD Shutdown latch pulldown resistance Resistor in series with an external pull-down NFET 2 kΩ
SOFT START and FORCED PWM and DIODE EMULATION PRGRAMMING (SS/DEM1, SS/DEM2)
ISS SS charging current source during startup VSS  ≤ 3.3V,  VEN > 2V, VUVLO > 2.5V, DIR < 1 or DIR > 2 63 70 77 µA
ISS SS charging current source after startup VSS  ≥ 3.9V,  VEN > 2V, VUVLO > 2.5V, DIR < 1 or DIR > 2 45 50 55 µA
SS to gm input offset 0.8 1 1.3 V
RSS SS discharge device Rds(ON) VSS = 2V 5 20 30 Ω
VSS_LOW SS discharge completion threshold Once it is discharged by internal logic 0.15 0.3 0.35 V
CONFIGURATIONS (CFG)
RCFG1 I2C Address: b0100000. IMON = IMON_IL 0 kΩ
RCFG2 I2C Address: b0100001. IMON = IMON_IL 0.316 0.324 kΩ
RCFG3 I2C Address: b0100010. IMON = IMON_IL 0.649 0.665 kΩ
RCFG4 I2C Address: b0100011. IMON = IMON_IL 1.1 1.13 kΩ
RCFG5 I2C Address: b0100100. IMON = IMON_IL 1.65 1.69 kΩ
RCFG6 I2C Address: b0100101. IMON = IMON_IL 2.43 2.49 kΩ
RCFG7 I2C Address: b0100110. IMON = IMON_IL 3.32 3.4 kΩ
RCFG8 I2C Address: b0100111. IMON = IMON_IL 4.53 4.64 kΩ
RCFG9 I2C Address: b0100111. IMON = IMON_BSTOUT 6.65 6.81 kΩ
RCFG10 I2C Address: b0100110. IMON = IMON_BSTOUT 10.2 10.5 kΩ
RCFG11 I2C Address: b0100101. IMON = IMON_BSTOUT 13.7 14.0 kΩ
RCFG12 I2C Address: b0100100. IMON = IMON_BSTOUT 18.7 19.1 kΩ
RCFG13 I2C Address: b0100011. IMON = IMON_BSTOUT 26.1 26.7 kΩ
RCFG14 I2C Address: b0100010. IMON = IMON_BSTOUT 37.4 38.3 kΩ
RCFG15 I2C Address: b0100001. IMON = IMON_BSTOUT 60.4 61.9 kΩ
RCFG16 I2C Address: b0100000. IMON = IMON_BSTOUT 95.3 97.6 kΩ
I2C INTERFACE (SLC, SDA)
VSDAL SDA input low state 1.0 V
VSDAH SDA input high state 2.0 V
VSCLL SCL input low state 1.0 V
VSCLH SCL input high state 2.0 V
Thermal Shutdown
TJ_SD Thermal shutdown 155 175 ℃
Thermal shutdown hysteresis 15 ℃