SNVSC75B April   2023  – September 2025 LM5171-Q1

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Pin Configuration and Functions
  6. Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Typical Characteristics
  7. Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Bias Supplies and Voltage Reference (VCC, VDD, and VREF)
      2. 6.3.2  Undervoltage Lockout (UVLO)
      3. 6.3.3  Device Configurations (CFG)
      4. 6.3.4  High Voltage Inputs (HV1, HV2)
      5. 6.3.5  Current Sense Amplifier
      6. 6.3.6  Control Commands
        1. 6.3.6.1 Channel Enable Commands (EN1, EN2)
        2. 6.3.6.2 Direction Command (DIR1 and DIR2)
        3. 6.3.6.3 Channel Current Setting Commands (ISET1 and ISET2)
      7. 6.3.7  Channel Current Monitor (IMON1, IMON2)
        1. 6.3.7.1 Individual Channel Current Monitor
        2. 6.3.7.2 Multiphase Total Current Monitoring
      8. 6.3.8  Cycle-by-Cycle Peak Current Limit (IPK)
      9. 6.3.9  Inner Current Loop Error Amplifier
      10. 6.3.10 Outer Voltage Loop Error Amplifier
      11. 6.3.11 Soft Start, Diode Emulation, and Forced PWM Control (SS/DEM1 and SS/DEM2)
        1. 6.3.11.1 ISET Soft-Start Control by the SS/DEM Pins
        2. 6.3.11.2 DEM Programming
        3. 6.3.11.3 FPWM Programming and Dynamic FPWM and DEM Change
      12. 6.3.12 Gate Drive Outputs, Dead Time Programming and Adaptive Dead Time (HO1, HO2, LO1, LO2, DT/SD)
      13. 6.3.13 Emergency Latched Shutdown (DT/SD)
      14. 6.3.14 PWM Comparator
      15. 6.3.15 Oscillator (OSC)
      16. 6.3.16 Synchronization to an External Clock (SYNCI, SYNCO)
      17. 6.3.17 Overvoltage Protection (OVP)
      18. 6.3.18 Multiphase Configurations (SYNCO, OPT)
        1. 6.3.18.1 Multiphase in Star Configuration
        2. 6.3.18.2 Daisy-Chain Configurations for 2, 3, or 4 Phases parallel operations
        3. 6.3.18.3 Daisy-Chain configuration for 6 or 8 phases parallel operation
      19. 6.3.19 Thermal Shutdown
    4. 6.4 Device Functional Modes
      1. 6.4.1 Initialization Mode
      2. 6.4.2 Standby Mode
      3. 6.4.3 Power Delivery Mode
      4. 6.4.4 Shutdown Mode
      5. 6.4.5 Latched Shutdown mode
  8. Registers
    1. 7.1 I2C Serial Interface
    2. 7.2 I2C Bus Operation
    3. 7.3 Clock Stretching
    4. 7.4 Data Transfer Formats
    5. 7.5 Single READ From a Defined Register Address
    6. 7.6 Sequential READ Starting From a Defined Register Address
    7. 7.7 Single WRITE to a Defined Register Address
    8. 7.8 Sequential WRITE Starting From A Defined Register Address
    9. 7.9 REGFIELD Registers
  9. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Small Signal Model
        1. 8.1.1.1 Current Loop Small Signal Model
        2. 8.1.1.2 Current Loop Compensation
        3. 8.1.1.3 Voltage Loop Small Signal Model
        4. 8.1.1.4 Voltage Loop Compensation
    2. 8.2 PWM to ISET Pins
    3. 8.3 ISET Clamp
    4. 8.4 Dynamic Dead Time Adjustment
    5. 8.5 Proper Termination of Unused Pins
    6. 8.6 Typical Application
      1. 8.6.1 60A, Dual-Phase, 48V to 12V Bidirectional Converter
        1. 8.6.1.1 Design Requirements
        2. 8.6.1.2 Detailed Design Procedure
          1. 8.6.1.2.1  Determining the Duty Cycle
          2. 8.6.1.2.2  Oscillator Programming (OSC)
          3. 8.6.1.2.3  Power Inductor, RMS and Peak Currents
          4. 8.6.1.2.4  Current Sense (RCS)
          5. 8.6.1.2.5  Current Setting Commands (ISETx)
          6. 8.6.1.2.6  Peak Current Limit (IPK)
          7. 8.6.1.2.7  Power MOSFETS
          8. 8.6.1.2.8  Bias Supply
          9. 8.6.1.2.9  Boot Strap Capacitor
          10. 8.6.1.2.10 Overvoltage Protection (OVP)
          11. 8.6.1.2.11 Dead Time (DT/SD)
          12. 8.6.1.2.12 Channel Current Monitor (IMONx)
          13. 8.6.1.2.13 Undervoltage Lockout (UVLO)
          14. 8.6.1.2.14 HVx Pin Configuration
          15. 8.6.1.2.15 Loop Compensation
          16. 8.6.1.2.16 Soft Start (SS/DEMx)
        3. 8.6.1.3 Application Curves
          1. 8.6.1.3.1 Efficiency and Thermal Performance
          2. 8.6.1.3.2 Step Load Response
          3. 8.6.1.3.3 Dual-Channel Interleaving Operation
          4. 8.6.1.3.4 Typical Start Up and Shutdown
          5. 8.6.1.3.5 DEM and FPWM
          6. 8.6.1.3.6 Mode Transition Between DEM and FPWM
          7. 8.6.1.3.7 ISET Tracking and Pre-charge
          8. 8.6.1.3.8 Protections
    7. 8.7 Power Supply Recommendations
    8. 8.8 Layout
      1. 8.8.1 Layout Guidelines
      2. 8.8.2 Layout Examples
  10. Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Current Loop Small Signal Model

Figure 8-1 shows the current loop block diagram of each phase in buck mode. VHV is the input while VLV is the output.

LM5171-Q1 Buck Loop Block
          Diagram Figure 8-1 Buck Loop Block Diagram

The inner current loop is designed first. The average current-mode control loop of buck mode is modeled in Figure 8-2.

LM5171-Q1 Current Loop
          Block Diagram Figure 8-2 Current Loop Block Diagram

The buck mode duty cycle (d) to channel inductor current (iLm) transfer function is determined by the following:

Equation 16. G i d _ B K s = i ^ L m d ^ = V H V R O U T _ B K × 1 + s ω Z _ i l _ B K 1 + s ω 0 _ B K × Q B K + s 2 ω 0 _ B K 2

where

Equation 17. R O U T _ B K = V L V n p × I L m a x
Equation 18. ω Z _ i l _ B K = 1 R O U T _ B K × C O U T _ B K
Equation 19. ω 0 _ B K = 1 L m × C O U T _ B K
Equation 20. Q B K = 1 ω 0 _ B K × 1 L m R O U T _ B K + R E S R _ B K + R C S + R S × C O U T _ B K
  • Lm is the power inductor,
  • RCS is the current sense resistor,
  • RS is the equivalent total resistance along the current path excluding RCS,
  • COUT_BK is the total output capacitance in buck mode.
  • RESR_BK is the total output capacitor equivalent series resistance (ESR).

Figure 8-3 shows the current loop block diagram in boost mode. VLV is the input while VHV is the output.

LM5171-Q1 Boost Loop Block Diagram Figure 8-3 Boost Loop Block Diagram

The average current-mode control loop of boost mode is the same as buck as shown in Figure 8-2. But the transfer function of the boost power stage Gid(s) and Gvd(s) is different from that of buck power stage.

The boost mode duty cycle (d) to channel inductor current (iLm) transfer function is determined by the following:

Equation 21. G i d _ B S T s = i ^ L m d ^ = 2 × V L V D ' 3 × R O U T _ B S T × 1 + s ω Z _ i l _ B S T 1 + s ω 0 _ B S T × Q B S T + s 2 ω 0 _ B S T 2

where

Equation 22. D ' = V L V V H V
Equation 23. R O U T _ B S T = V H V 2 V L V × I L m a x
Equation 24. ω Z _ i l _ B S T = 2 R O U T _ B S T × C O U T _ B S T
Equation 25. ω 0 _ B S T = D ' L m × C O U T _ B S T
Equation 26. Q B S T = D ' ω 0 _ B S T × 1 L m D ' × R O U T _ B S T + R C S + R S × C O U T _ B S T D ' + R E S R _ B S T × C O U T _ B S T
  • COUT_BST is the total output capacitance for each phase in boost mode.
  • RESR_BST is the total output capacitor equivalent series resistance (ESR) for each phase in boost mode.

When we select the current loop cross over frequency at 1/6 of switching frequency, Gid_BK(s) is simplified. For the numerator, s×ROUT_BK×COUT_BK dominates. And for the denominator, s20_BK2 dominates. Equation 16 is simplified as:

Equation 27. G i d _ B K s = V H V R O U T _ B K × 1 + s ω Z _ i l _ B K s 2 ω 0 _ B K 2 = V H V s × L m

Similarly, Equation 21 is simplified as:

Equation 28. G i d _ B S T s = 2 × V L V D ' 3 × R O U T _ B S T × s ω Z _ i l _ B S T s 2 ω 0 _ B S T 2 = V H V s × L m

From Equation 27 and Equation 28, the same duty cycle (d) to channel inductor current (iLm) transfer function is shared by both buck and boost mode:

Equation 29. G i d s = V H V s × L m

So compensator for buck current loop and boost current loop is also shared.