SNVSC75B April   2023  – September 2025 LM5171-Q1

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Pin Configuration and Functions
  6. Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Typical Characteristics
  7. Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Bias Supplies and Voltage Reference (VCC, VDD, and VREF)
      2. 6.3.2  Undervoltage Lockout (UVLO)
      3. 6.3.3  Device Configurations (CFG)
      4. 6.3.4  High Voltage Inputs (HV1, HV2)
      5. 6.3.5  Current Sense Amplifier
      6. 6.3.6  Control Commands
        1. 6.3.6.1 Channel Enable Commands (EN1, EN2)
        2. 6.3.6.2 Direction Command (DIR1 and DIR2)
        3. 6.3.6.3 Channel Current Setting Commands (ISET1 and ISET2)
      7. 6.3.7  Channel Current Monitor (IMON1, IMON2)
        1. 6.3.7.1 Individual Channel Current Monitor
        2. 6.3.7.2 Multiphase Total Current Monitoring
      8. 6.3.8  Cycle-by-Cycle Peak Current Limit (IPK)
      9. 6.3.9  Inner Current Loop Error Amplifier
      10. 6.3.10 Outer Voltage Loop Error Amplifier
      11. 6.3.11 Soft Start, Diode Emulation, and Forced PWM Control (SS/DEM1 and SS/DEM2)
        1. 6.3.11.1 ISET Soft-Start Control by the SS/DEM Pins
        2. 6.3.11.2 DEM Programming
        3. 6.3.11.3 FPWM Programming and Dynamic FPWM and DEM Change
      12. 6.3.12 Gate Drive Outputs, Dead Time Programming and Adaptive Dead Time (HO1, HO2, LO1, LO2, DT/SD)
      13. 6.3.13 Emergency Latched Shutdown (DT/SD)
      14. 6.3.14 PWM Comparator
      15. 6.3.15 Oscillator (OSC)
      16. 6.3.16 Synchronization to an External Clock (SYNCI, SYNCO)
      17. 6.3.17 Overvoltage Protection (OVP)
      18. 6.3.18 Multiphase Configurations (SYNCO, OPT)
        1. 6.3.18.1 Multiphase in Star Configuration
        2. 6.3.18.2 Daisy-Chain Configurations for 2, 3, or 4 Phases parallel operations
        3. 6.3.18.3 Daisy-Chain configuration for 6 or 8 phases parallel operation
      19. 6.3.19 Thermal Shutdown
    4. 6.4 Device Functional Modes
      1. 6.4.1 Initialization Mode
      2. 6.4.2 Standby Mode
      3. 6.4.3 Power Delivery Mode
      4. 6.4.4 Shutdown Mode
      5. 6.4.5 Latched Shutdown mode
  8. Registers
    1. 7.1 I2C Serial Interface
    2. 7.2 I2C Bus Operation
    3. 7.3 Clock Stretching
    4. 7.4 Data Transfer Formats
    5. 7.5 Single READ From a Defined Register Address
    6. 7.6 Sequential READ Starting From a Defined Register Address
    7. 7.7 Single WRITE to a Defined Register Address
    8. 7.8 Sequential WRITE Starting From A Defined Register Address
    9. 7.9 REGFIELD Registers
  9. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Small Signal Model
        1. 8.1.1.1 Current Loop Small Signal Model
        2. 8.1.1.2 Current Loop Compensation
        3. 8.1.1.3 Voltage Loop Small Signal Model
        4. 8.1.1.4 Voltage Loop Compensation
    2. 8.2 PWM to ISET Pins
    3. 8.3 ISET Clamp
    4. 8.4 Dynamic Dead Time Adjustment
    5. 8.5 Proper Termination of Unused Pins
    6. 8.6 Typical Application
      1. 8.6.1 60A, Dual-Phase, 48V to 12V Bidirectional Converter
        1. 8.6.1.1 Design Requirements
        2. 8.6.1.2 Detailed Design Procedure
          1. 8.6.1.2.1  Determining the Duty Cycle
          2. 8.6.1.2.2  Oscillator Programming (OSC)
          3. 8.6.1.2.3  Power Inductor, RMS and Peak Currents
          4. 8.6.1.2.4  Current Sense (RCS)
          5. 8.6.1.2.5  Current Setting Commands (ISETx)
          6. 8.6.1.2.6  Peak Current Limit (IPK)
          7. 8.6.1.2.7  Power MOSFETS
          8. 8.6.1.2.8  Bias Supply
          9. 8.6.1.2.9  Boot Strap Capacitor
          10. 8.6.1.2.10 Overvoltage Protection (OVP)
          11. 8.6.1.2.11 Dead Time (DT/SD)
          12. 8.6.1.2.12 Channel Current Monitor (IMONx)
          13. 8.6.1.2.13 Undervoltage Lockout (UVLO)
          14. 8.6.1.2.14 HVx Pin Configuration
          15. 8.6.1.2.15 Loop Compensation
          16. 8.6.1.2.16 Soft Start (SS/DEMx)
        3. 8.6.1.3 Application Curves
          1. 8.6.1.3.1 Efficiency and Thermal Performance
          2. 8.6.1.3.2 Step Load Response
          3. 8.6.1.3.3 Dual-Channel Interleaving Operation
          4. 8.6.1.3.4 Typical Start Up and Shutdown
          5. 8.6.1.3.5 DEM and FPWM
          6. 8.6.1.3.6 Mode Transition Between DEM and FPWM
          7. 8.6.1.3.7 ISET Tracking and Pre-charge
          8. 8.6.1.3.8 Protections
    7. 8.7 Power Supply Recommendations
    8. 8.8 Layout
      1. 8.8.1 Layout Guidelines
      2. 8.8.2 Layout Examples
  10. Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Voltage Loop Small Signal Model

When the current loop compensator is designed, the outer voltage loop is then analyzed.

A system with np phases is shown in Figure 8-4.

LM5171-Q1 np phases system Figure 8-4 np phases system

The equivalent inductance and resistance are determined by

Equation 43. L m n p = L m n p
Equation 44. R S n p = R S n p
Equation 45. R C S n p = R C S n p
Equation 46. R f n p = R f n p

The buck mode duty cycle (d) to np phases inductor current transfer function is determined by the following:

Equation 47. G i d n p _ B K s = n p × i ^ L m d ^ = V H V R O U T _ B K × 1 + s ω Z _ i l _ B K 1 + s ω 0 n p _ B K × Q n p B K + s 2 ω 0 n p _ B K 2

where

Equation 48. R O U T _ B K = V L V n p × I L m a x
Equation 49. ω Z _ i l _ B K = 1 R O U T _ B K × C O U T _ B K
Equation 50. ω 0 n p _ B K = 1 L m n p × C O U T _ B K
Equation 51. Q n p B K = 1 ω 0 n p _ B K × 1 L m n p R O U T _ B K + R E S R _ B K + R C S n p + R S n p × C O U T _ B K

For np phase, the equivalent open loop gain Tinp(s) is obtained as

Equation 52. T i n p s = G c i s × 1 V M × G i d s × R f n p

where

Figure 8-5 shows the outer voltage control loop and inner current loop.

LM5171-Q1 Voltage Loop and Current Loop
                    Block Diagram Figure 8-5 Voltage Loop and Current Loop Block Diagram

The ISET to output voltage (vO) close loop transfer function is obtained as:

Equation 53. G v s s = v ^ L V v ^ I S E T = G c i s × 1 V M × G v d s 1 + T i n p s

When selecting the crossover frequency of the buck voltage loop lower than the current loop crossover frequency, Gvs(s) is simplified. For the denominator, Tinp(s) dominates, Equation 53 is written as:

Equation 54. G v s s = v ^ L V v ^ I S E T = G c i s × 1 V M × G v d s T i n p s = G v d s G i d s × R f n p

The buck power plant duty cycle (d) to output voltage (vLV) transfer function is determined by :

Equation 55. G v d _ B K s = v ^ L V d ^ = V H V × 1 + s ω Z _ v l _ B K 1 + s ω 0 n p _ B K × Q n p B K + s 2 ω 0 n p _ B K 2

where

Equation 56. ω Z _ v l _ B K = 1 R E S R _ B K × C O U T _ B K

Substituting Equation 55 into Equation 54, a simplified ISET to output voltage (VLV) transfer function is determined by the following:

Equation 57. G v s _ B K s = v ^ L V v ^ I S E T = K d c _ B K × 1 + s ω Z _ v l _ B K 1 + s ω Z _ i l _ B K

where

Equation 58. K d c _ B K = R O U T _ B K R f n p

Similarly, the boost power plant duty cycle (d) to output voltage (vHV) transfer function is determined by :

Equation 59. G v d _ B S T s = v ^ H V d ^ = V L V D ' 2 × 1 + s ω Z _ v l _ B S T 1 - s ω R H P Z 1 + s ω 0 n p _ B S T × Q n p B S T + s 2 ω 0 n p _ B S T 2

where

Equation 60. ω Z _ v l _ B S T = 1 R E S R _ B S T × C O U T _ B S T
Equation 61. ω R H P Z = R O U T _ B S T × D ' 2 L m n p

Substituting Equation 59 into Equation 54, a simplified ISET to output voltage (VHV) transfer function is determined by the following:

Equation 62. G v s _ B S T s = v ^ H V i ^ s e t = K d c _ B S T × 1 + s ω Z _ v l _ B S T 1 - s ω R H P Z 1 + s ω Z _ i l _ B S T

where

Equation 63. K d c _ B S T = R O U T _ B S T × D ' 2 × R f n p