SNVSC75B April   2023  – September 2025 LM5171-Q1

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Pin Configuration and Functions
  6. Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Typical Characteristics
  7. Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Bias Supplies and Voltage Reference (VCC, VDD, and VREF)
      2. 6.3.2  Undervoltage Lockout (UVLO)
      3. 6.3.3  Device Configurations (CFG)
      4. 6.3.4  High Voltage Inputs (HV1, HV2)
      5. 6.3.5  Current Sense Amplifier
      6. 6.3.6  Control Commands
        1. 6.3.6.1 Channel Enable Commands (EN1, EN2)
        2. 6.3.6.2 Direction Command (DIR1 and DIR2)
        3. 6.3.6.3 Channel Current Setting Commands (ISET1 and ISET2)
      7. 6.3.7  Channel Current Monitor (IMON1, IMON2)
        1. 6.3.7.1 Individual Channel Current Monitor
        2. 6.3.7.2 Multiphase Total Current Monitoring
      8. 6.3.8  Cycle-by-Cycle Peak Current Limit (IPK)
      9. 6.3.9  Inner Current Loop Error Amplifier
      10. 6.3.10 Outer Voltage Loop Error Amplifier
      11. 6.3.11 Soft Start, Diode Emulation, and Forced PWM Control (SS/DEM1 and SS/DEM2)
        1. 6.3.11.1 ISET Soft-Start Control by the SS/DEM Pins
        2. 6.3.11.2 DEM Programming
        3. 6.3.11.3 FPWM Programming and Dynamic FPWM and DEM Change
      12. 6.3.12 Gate Drive Outputs, Dead Time Programming and Adaptive Dead Time (HO1, HO2, LO1, LO2, DT/SD)
      13. 6.3.13 Emergency Latched Shutdown (DT/SD)
      14. 6.3.14 PWM Comparator
      15. 6.3.15 Oscillator (OSC)
      16. 6.3.16 Synchronization to an External Clock (SYNCI, SYNCO)
      17. 6.3.17 Overvoltage Protection (OVP)
      18. 6.3.18 Multiphase Configurations (SYNCO, OPT)
        1. 6.3.18.1 Multiphase in Star Configuration
        2. 6.3.18.2 Daisy-Chain Configurations for 2, 3, or 4 Phases parallel operations
        3. 6.3.18.3 Daisy-Chain configuration for 6 or 8 phases parallel operation
      19. 6.3.19 Thermal Shutdown
    4. 6.4 Device Functional Modes
      1. 6.4.1 Initialization Mode
      2. 6.4.2 Standby Mode
      3. 6.4.3 Power Delivery Mode
      4. 6.4.4 Shutdown Mode
      5. 6.4.5 Latched Shutdown mode
  8. Registers
    1. 7.1 I2C Serial Interface
    2. 7.2 I2C Bus Operation
    3. 7.3 Clock Stretching
    4. 7.4 Data Transfer Formats
    5. 7.5 Single READ From a Defined Register Address
    6. 7.6 Sequential READ Starting From a Defined Register Address
    7. 7.7 Single WRITE to a Defined Register Address
    8. 7.8 Sequential WRITE Starting From A Defined Register Address
    9. 7.9 REGFIELD Registers
  9. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Small Signal Model
        1. 8.1.1.1 Current Loop Small Signal Model
        2. 8.1.1.2 Current Loop Compensation
        3. 8.1.1.3 Voltage Loop Small Signal Model
        4. 8.1.1.4 Voltage Loop Compensation
    2. 8.2 PWM to ISET Pins
    3. 8.3 ISET Clamp
    4. 8.4 Dynamic Dead Time Adjustment
    5. 8.5 Proper Termination of Unused Pins
    6. 8.6 Typical Application
      1. 8.6.1 60A, Dual-Phase, 48V to 12V Bidirectional Converter
        1. 8.6.1.1 Design Requirements
        2. 8.6.1.2 Detailed Design Procedure
          1. 8.6.1.2.1  Determining the Duty Cycle
          2. 8.6.1.2.2  Oscillator Programming (OSC)
          3. 8.6.1.2.3  Power Inductor, RMS and Peak Currents
          4. 8.6.1.2.4  Current Sense (RCS)
          5. 8.6.1.2.5  Current Setting Commands (ISETx)
          6. 8.6.1.2.6  Peak Current Limit (IPK)
          7. 8.6.1.2.7  Power MOSFETS
          8. 8.6.1.2.8  Bias Supply
          9. 8.6.1.2.9  Boot Strap Capacitor
          10. 8.6.1.2.10 Overvoltage Protection (OVP)
          11. 8.6.1.2.11 Dead Time (DT/SD)
          12. 8.6.1.2.12 Channel Current Monitor (IMONx)
          13. 8.6.1.2.13 Undervoltage Lockout (UVLO)
          14. 8.6.1.2.14 HVx Pin Configuration
          15. 8.6.1.2.15 Loop Compensation
          16. 8.6.1.2.16 Soft Start (SS/DEMx)
        3. 8.6.1.3 Application Curves
          1. 8.6.1.3.1 Efficiency and Thermal Performance
          2. 8.6.1.3.2 Step Load Response
          3. 8.6.1.3.3 Dual-Channel Interleaving Operation
          4. 8.6.1.3.4 Typical Start Up and Shutdown
          5. 8.6.1.3.5 DEM and FPWM
          6. 8.6.1.3.6 Mode Transition Between DEM and FPWM
          7. 8.6.1.3.7 ISET Tracking and Pre-charge
          8. 8.6.1.3.8 Protections
    7. 8.7 Power Supply Recommendations
    8. 8.8 Layout
      1. 8.8.1 Layout Guidelines
      2. 8.8.2 Layout Examples
  10. Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
Channel Current Monitor (IMONx)

For best current monitor accuracy, choose IMONx resistor that the maximum operating voltage on the IMONx pin is less than 3V.

Considering two phase current monitoring with maximum 50A for each channel, and make sure IMONx voltage no more than 3V, RIMONx is found as:

Equation 100. RIMONx = 10kΩ

Choose CIMONx considering delay and voltage ripple. Here we select:

Equation 101. CIMONx = 10nF

Then the delay of the monitor is determined by the following time constant:

Equation 102. τIMONx=RIMONx×CIMONx=10kΩ×10ns=100μs

At full load, the DC component of the monitor voltage is:

Equation 103. VIMONx=2×Imax×RCS500Ω+50μA×RIMONx=2×30A×1mΩ500Ω+50μA×10kΩ=2.2V

Considering the inductor ripple current, the IOUT peak to peak ripple current is:

Equation 104. Δ I M O N x = I p k - p k × R C S 500 Ω = 23.8 A × 1 m Ω 500 Ω = 47.6 μ A

The RC filter corner frequency is thus given by:

Equation 105. fIMONx=12π×RIMONx×CIMONx=16.28×10kΩ×10nF=1.59kHz

The resulting peak-to-peak monitor ripple voltage is approximately determined by:

Equation 106. ΔVIMONx=ΔIMONx×RIMONx12i×π×FSW×CIMONx=47.6μA×10kΩ12i×π×100kHz×10nF=7.5mV

The peak-to-peak monitor ripple voltage is approximately 0.34% of the full load DC monitor voltage. Increasing CIMONx attenuates the ripple voltage at the cost of higher monitor delay.