SNVSC75B April   2023  – September 2025 LM5171-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Bias Supplies and Voltage Reference (VCC, VDD, and VREF)
      2. 6.3.2  Undervoltage Lockout (UVLO)
      3. 6.3.3  Device Configurations (CFG)
      4. 6.3.4  High Voltage Inputs (HV1, HV2)
      5. 6.3.5  Current Sense Amplifier
      6. 6.3.6  Control Commands
        1. 6.3.6.1 Channel Enable Commands (EN1, EN2)
        2. 6.3.6.2 Direction Command (DIR1 and DIR2)
        3. 6.3.6.3 Channel Current Setting Commands (ISET1 and ISET2)
      7. 6.3.7  Channel Current Monitor (IMON1, IMON2)
        1. 6.3.7.1 Individual Channel Current Monitor
        2. 6.3.7.2 Multiphase Total Current Monitoring
      8. 6.3.8  Cycle-by-Cycle Peak Current Limit (IPK)
      9. 6.3.9  Inner Current Loop Error Amplifier
      10. 6.3.10 Outer Voltage Loop Error Amplifier
      11. 6.3.11 Soft Start, Diode Emulation, and Forced PWM Control (SS/DEM1 and SS/DEM2)
        1. 6.3.11.1 ISET Soft-Start Control by the SS/DEM Pins
        2. 6.3.11.2 DEM Programming
        3. 6.3.11.3 FPWM Programming and Dynamic FPWM and DEM Change
      12. 6.3.12 Gate Drive Outputs, Dead Time Programming and Adaptive Dead Time (HO1, HO2, LO1, LO2, DT/SD)
      13. 6.3.13 Emergency Latched Shutdown (DT/SD)
      14. 6.3.14 PWM Comparator
      15. 6.3.15 Oscillator (OSC)
      16. 6.3.16 Synchronization to an External Clock (SYNCI, SYNCO)
      17. 6.3.17 Overvoltage Protection (OVP)
      18. 6.3.18 Multiphase Configurations (SYNCO, OPT)
        1. 6.3.18.1 Multiphase in Star Configuration
        2. 6.3.18.2 Daisy-Chain Configurations for 2, 3, or 4 Phases parallel operations
        3. 6.3.18.3 Daisy-Chain configuration for 6 or 8 phases parallel operation
      19. 6.3.19 Thermal Shutdown
    4. 6.4 Device Functional Modes
      1. 6.4.1 Initialization Mode
      2. 6.4.2 Standby Mode
      3. 6.4.3 Power Delivery Mode
      4. 6.4.4 Shutdown Mode
      5. 6.4.5 Latched Shutdown mode
  8. 7 Registers
    1. 7.1 I2C Serial Interface
    2. 7.2 I2C Bus Operation
    3. 7.3 Clock Stretching
    4. 7.4 Data Transfer Formats
    5. 7.5 Single READ From a Defined Register Address
    6. 7.6 Sequential READ Starting From a Defined Register Address
    7. 7.7 Single WRITE to a Defined Register Address
    8. 7.8 Sequential WRITE Starting From A Defined Register Address
    9. 7.9 REGFIELD Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Small Signal Model
        1. 8.1.1.1 Current Loop Small Signal Model
        2. 8.1.1.2 Current Loop Compensation
        3. 8.1.1.3 Voltage Loop Small Signal Model
        4. 8.1.1.4 Voltage Loop Compensation
    2. 8.2 PWM to ISET Pins
    3. 8.3 ISET Clamp
    4. 8.4 Dynamic Dead Time Adjustment
    5. 8.5 Proper Termination of Unused Pins
    6. 8.6 Typical Application
      1. 8.6.1 60A, Dual-Phase, 48V to 12V Bidirectional Converter
        1. 8.6.1.1 Design Requirements
        2. 8.6.1.2 Detailed Design Procedure
          1. 8.6.1.2.1  Determining the Duty Cycle
          2. 8.6.1.2.2  Oscillator Programming (OSC)
          3. 8.6.1.2.3  Power Inductor, RMS and Peak Currents
          4. 8.6.1.2.4  Current Sense (RCS)
          5. 8.6.1.2.5  Current Setting Commands (ISETx)
          6. 8.6.1.2.6  Peak Current Limit (IPK)
          7. 8.6.1.2.7  Power MOSFETS
          8. 8.6.1.2.8  Bias Supply
          9. 8.6.1.2.9  Boot Strap Capacitor
          10. 8.6.1.2.10 Overvoltage Protection (OVP)
          11. 8.6.1.2.11 Dead Time (DT/SD)
          12. 8.6.1.2.12 Channel Current Monitor (IMONx)
          13. 8.6.1.2.13 Undervoltage Lockout (UVLO)
          14. 8.6.1.2.14 HVx Pin Configuration
          15. 8.6.1.2.15 Loop Compensation
          16. 8.6.1.2.16 Soft Start (SS/DEMx)
        3. 8.6.1.3 Application Curves
          1. 8.6.1.3.1 Efficiency and Thermal Performance
          2. 8.6.1.3.2 Step Load Response
          3. 8.6.1.3.3 Dual-Channel Interleaving Operation
          4. 8.6.1.3.4 Typical Start Up and Shutdown
          5. 8.6.1.3.5 DEM and FPWM
          6. 8.6.1.3.6 Mode Transition Between DEM and FPWM
          7. 8.6.1.3.7 ISET Tracking and Pre-charge
          8. 8.6.1.3.8 Protections
    7. 8.7 Power Supply Recommendations
    8. 8.8 Layout
      1. 8.8.1 Layout Guidelines
      2. 8.8.2 Layout Examples
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

4 Pin Configuration and Functions

LM5171-Q1 LM5171-Q1 PHP Package, 48-Pin TQFP (Top View) Figure 4-1 LM5171-Q1 PHP Package, 48-Pin TQFP (Top View)
Table 4-1 Pin Functions
PINI/O#T4611898-2DESCRIPTION
NO.NAME
1VREFPOutput of the built-in 3.5V +/- 1% reference voltage. Connect a 0.1μF capacitor between the VREF pin and AGND.
2FBLVIInverting input of the error amplifier for buck mode. This error amplifier is active when DIR1 is high. Short FBLV and ERRLV when this amplifier is not used.
3ERRLVOOutput of the error amplifier for buck mode. This error amplifier is active when DIR1 is high. Short FBLV and ERRLV when this amplifier is not used.
4IMON2OCH-2 current monitor pin. A current source flows out of this pin. The current source is proportional to the CH-2 inductor current or CH-2 boost mode output current based on CFG selection. Placing a terminating resistor and filter capacitor from IMON2 to AGND produces a DC voltage representing the CH-2 DC current level. An internal 50μA offset DC current source at the IMON2 pin raises the active signal above the ground noise, thus improving the monitor noise immunity.
5CSA2ICH-2 differential current sense inputs. The CH-2 current sense resistor is placed between these two pins. The CSA2 pin connects to the power inductor and CSB2 pin connects to the LV-Port.
6CSB2I
7ISET2ICH-2 current programming pin. There is 1V offset on ISET2, that is, the CH-2 inductor current is proportional to (ISET2-1V). In DEM, the inductor current is 0 when ISET2 is less than1V. In FPWM, the inductor current reverses when ISET2 is less than 1V.
8COMP2OOutput of the CH-2 transconductance (gm) error amplifier and the inverting input of the CH-2 PWM comparator. Connect a loop compensation network to this pin.
9SS/DEM2IISET2 soft-start pin. The SS/DEM2-pin also sets CH-2 in either DEM or FPWM. An external capacitor sets the ramp rate of the SS/DEM2 pin voltage during soft start. SS/DEM2 overrides ISET2 voltage during soft-start. When an outer voltage loop is used, use 100pF soft-start capacitor. A 60.4kΩ resistor between SS/DEM2 and AGND sets CH-2 to DEM. CH-2 operates in FPWM without the resistor.
10EN2ICH-2 enable pin. Pulling EN2 above 2V turns off the SS/DEM2 pulldown and allows CH-2 to begin a soft-start sequence. Pulling EN2 below 1 V discharges the SS/DEM2 capacitor and holds it low. The high side and low side gate drivers of both channels are held in the low state when SS/DEM2 is discharged.
11DIR2ICH-2 direction command input. Pulling DIR2 pin above 2V sets the converter to buck mode. Pulling DIR2 below 1V sets the converter to the boost mode. If the DIR2 pin is left open, the device detects an invalid command and disables CH-2 with the MOSFET gate drivers in the low state.
12VDDPOutput of 5V internal LDO. Connect a 1μF capacitor between the VDD pin and AGND.
13HV2IConnect to HV-Port for CH-2 controller.
14HB2ICH-2 high-side gate driver bootstrap supply. Connect a 0.22μF capacitor between the pin and SW2. Connect a Zener diode between the pin and SW2 to protect the high side driver from overvoltage.
15HO2OCH-2 high-side gate driver output. Connect to the gate of the high-side N-channel MOSFET through a short, low inductance path.
16SW2PCH-2 switching node. Connect directly to the source of the high-side N-channel MOSFET.
17LO2OCH-2 low-side gate driver output. Connect to the gate of the low-side N-channel MOSFET through a short, low inductance path.
18PGNDGPower ground connection pin for low-side gate drivers and VCC bias supply.
19VCCPVCC bias supply pin. Connect a 2.2μF capacitor between the VCC pin and AGND.
20LO1OCH-1 low-side gate driver output. Connect to the gate of the low-side N-channel MOSFET through a short, low inductance path.
21SW1PCH-1 switch node. Connect directly to the source of the high-side N-channel MOSFET.
22HO1OCH-1 high-side gate driver output. Connect to the gate of the high-side N-channel MOSFET through a short, low inductance path.
23HB1ICH-1 high-side gate driver bootstrap supply input. Connect a 0.22μF capacitor between the pin and SW1. Connect a Zener diode between the pin and SW1 to protect the high side driver from overvoltage.
24HV1IConnect to the HV-Port for CH-1 controller.
25LDODRVOThe LDO MOSFET driver. Connect to the LDO MOSFET gate to get a regulated 9V VCC. Leave this pin open when it is not used.
26DIR1ICH-1 direction command input. Pulling DIR1 pin above 2V sets the converter to buck mode. Pulling DIR1 below 1V sets the converter to the boost mode. If the DIR1 pin is left open, the device detects an invalid command and disables CH-1 with the MOSFET gate drivers in the low state.
27EN1ICH-1 enable pin. Pulling EN1 above 2V turns off the SS1 pulldown and allows CH-1 to begin a soft-start sequence. Pulling EN1 below 1 V discharges the SS1 capacitor and holds it low. The high side and low side gate drivers of both channels are held in the low state when SS1 is discharged.
28SS/DEM1IISET1 soft-start pin. The SS/DEM1-pin also sets CH-1 in either DEM or FPWM. An external capacitor sets the ramp rate of the SS/DEM1 pin voltage during soft start. SS/DEM1 overrides ISET1 voltage during soft-start. When an outer voltage loop is used, use 100pF soft-start capacitor. A 60.4kΩ resistor between SS/DEM1 and AGND sets CH-1 to DEM. CH-1 operates in FPWM without the resistor.
29COMP1OOutput of the CH-1 trans-conductance (gm) error amplifier and the inverting input of the CH-1 PWM comparator. Connect a loop compensation network to this pin.
30ISET1ICH-1 current programming pin. There is 1V offset on ISET1, that is, the CH-1 inductor current is proportional to (ISET1-1V). In DEM, the inductor current is 0 when ISET1 is less than1V. In FPWM, the inductor current reverses when ISET1 is less than 1V.
31CSB1ICH-1 differential current sense inputs. The CH-1 current sense resistor is placed between these two pins. The CSA1 pin connects to the power inductor and CSB1 pin connects to the LV-Port.
32CSA1I
33IMON1OCH-1 current monitor pin. A current source flows out of this pin. The current source is proportional to the CH-1 inductor current or CH-1 boost mode output current based on CFG selection. Placing a terminating resistor and filter capacitor from IMON1 to AGND produces a DC voltage representing the CH-1 DC current level. An internal 50μA offset DC current source at the IMON1 pin raises the active signal above the ground noise, thus improving the monitor noise immunity.
34ERRHVOOutput of the error amplifier for boost mode. This error amplifier is active when DIR1 is low.
35FBHVIInverting input of the error amplifier for boost mode. This error amplifier is active when DIR1 is low.
36OVPIThe inverting input of internal overvoltage comparator. When the OVP pin voltage rises above 1V, the SS/DEM1 and VSET capacitors are discharged and held low until the OVP pin drops to 0.9V.
37SDAI/OData of I2C interface. Pull to VDD through a 10kΩ resistor if SDA is not used.
38SCLIClock of I2C interface. Pull to VDD through a 10kΩ resistor if SCL is not used.
39SYNCOOClock synchronization output pin. Connect SYNCO to the downstream device SYNCI for 3-phase or 4-phase configuration. Leave this pin open when it is not used.
40SYNCIIInput for an external clock that overrides the free-running internal oscillator. Connect the SYNCI pin to ground when not used. Ground the SYNCI pin or leave it open when it is not used.
41OPTIMultiphase configuration pin. Tie OPT pin to VDD for 4-phase operation. Tie OPT pin to AGND for 3-phase operation.
42OSCIThe internal oscillator frequency is programmed by a resistor between OSC and AGND.
43AGNDGAnalog ground reference. Connect AGND to PGND externally through a single point connection to improve the noise immunity.
44CFGIThe I2C address and IMON function selection pin.
45UVLOIThe UVLO pin serves as the primary enable pin. When UVLO is pulled below 1.25 V, the device is in a low quiescent current shutdown mode. When UVLO is pulled above 1.25 V but below 2.5 V, the device enters the initialization mode. LDODRV is turned on to control the external MOSFET to produce the VCC. The VDD and VREF are also established. When UVLO is pulled above the 2.5 V, the device is ready to operate.
46DT/SDIDead-time programming and emergent latched shutdown pin. A resistor connected between DT/SD and AGND sets the dead time between the high-side and low-side driver outputs. Tie the DT pin to VDD to activate the internal adaptive dead time control. When DT/SD pin is pulled low, the device enters latched shutdown.
47IPKIPeak current limit programming pin. IPK voltage sets the threshold for the cycle-by-cycle current limit comparator. Use a resistor divider from VREF to set IPK voltage.
48VSETIVoltage error amplifier reference input pin. The VSET pin is pulled low when the device is shutdown, EN1 is low or DIR1 flips. Use a resistor divider from VREF to set VSET pin voltage. Connect a capacitor to VSET for voltage loop soft-start.
—EP—Exposed pad of the package. Solder to the large ground plane to reduce thermal resistance.
(1) Note: G = Ground, I = Input, O = Output, P = Power