SPRY303F May 2019 – February 2025 AM3351 , AM3352 , AM3354 , AM3356 , AM3357 , AM3358 , AM3358-EP , AM3359 , AM4372 , AM4376 , AM4377 , AM4378 , AM4379 , AM5706 , AM5708 , AM5746 , AM5748 , AM623 , AM625 , AM625-Q1 , AM625SIP , AM62A1-Q1 , AM62A3 , AM62A3-Q1 , AM62A7 , AM62A7-Q1 , AM62L , AM62P , AM62P-Q1 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442 , AM6526 , AM6528 , AM6546 , AM6548 , AM68 , AM68A , AM69 , AM69A , DRA821U , DRA821U-Q1 , DRA829J , DRA829J-Q1 , DRA829V , DRA829V-Q1 , TDA4VM , TDA4VM-Q1
Hackers are quite adept at intercepting wireless or wired network communications. In fact, some communication protocols have known security weaknesses that have been exploited. Deploying only highly secure communication protocols often involves a significant number of processing cycles to encrypt and decrypt the communication stream, as well as verify the authenticity of the sender or receiver. Designers are sometimes faced with balancing communication throughput and security, but some embedded processors avoid this dilemma by integrating hardware-based accelerators for the cryptographic algorithms that are used in conjunction with standard communication protocols.
Figure 6 Secure storage.