TPS74201
- Input Voltage Range: 0.8 V to 5.5 V
- Soft-Start (SS) Pin Provides a Linear Start-Up With Ramp Time Set by External Capacitor
- 1% Accuracy Over Line, Load, and Temperature
- Supports Input Voltages as Low as 0.8 V With External Bias Supply
- Adjustable Output (0.8 V to 3.6 V)
- Ultra-Low Dropout: 55 mV at 1.5 A (Typical)
- Stable With Any or No Output Capacitor
- Excellent Transient Response
- Open-Drain Power-Good (VQFN)
- Active High Enable
The TPS742 series of low-dropout (LDO) linear regulators provide an easy-to-use, robust power-management solution for a wide variety of applications. User-programmable soft-start minimizes stress on the input power source by reducing capacitive inrush current on start-up. The soft-start is monotonic and well suited for powering many different types of processors and ASICs. The enable input and power-good output allow easy sequencing with external regulators. This complete flexibility permits the user to configure a solution that meets the sequencing requirements of FPGAs, DSPs, and other applications with special start-up requirements.
A precision reference and error amplifier deliver 1% accuracy over load, line, temperature, and process. Each LDO is stable with low-cost ceramic output capacitors, and the family is fully specified from –40°C to 125°C. The TPS742 devices are offered in a small 5-mm × 5-mm VQFN (RGW) and a small 3.5-mm × 3.5-mm VQFN (RGR) package, yielding a highly compact total solution size. For applications that require additional power dissipation, the DDPAK/TO-263 (KTW) package is also available.
技術文件
類型 | 標題 | 日期 | ||
---|---|---|---|---|
* | Data sheet | TPS742 1.5-A Ultra-LDO With Programmable Soft-Start datasheet (Rev. N) | PDF | HTML | 2016年 11月 17日 |
Application note | LDO Noise Demystified (Rev. B) | PDF | HTML | 2020年 8月 18日 | |
Application note | Using Thermal Calculation Tools for Analog Components (Rev. A) | 2019年 8月 30日 | ||
Application note | A Topical Index of TI LDO Application Notes (Rev. F) | 2019年 6月 27日 | ||
Application note | LDO PSRR Measurement Simplified (Rev. A) | PDF | HTML | 2017年 8月 9日 | |
Application note | LDO Performance Near Dropout | 2010年 10月 8日 | ||
Application note | Using New Thermal Metrics | 2009年 12月 15日 | ||
Analog Design Journal | Q3 2007 Issue Analog Applications Journal | 2007年 8月 10日 | ||
Analog Design Journal | Simultaneous power-down sequencing with the TPS74x01 family of linear regulators | 2007年 8月 10日 | ||
Analog Design Journal | A 3-A, 1.2-Vout linear regulator with 80% efficiency and Plost < 1W | 2006年 10月 10日 | ||
EVM User's guide | TPS74x01EVM-118 User's Guide | 2006年 6月 20日 |
設計與開發
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封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
---|---|---|
TO-263 (KTW) | 7 | Ultra Librarian |
VQFN (RGR) | 20 | Ultra Librarian |
VQFN (RGW) | 20 | Ultra Librarian |
訂購與品質
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
- 晶圓廠位置
- 組裝地點
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。