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線性與低壓差 (LDO) 穩壓器

TPS74201

現行

1.5-A、低 VIN (0.8-V)、低雜訊、高 PSRR、可調式超低壓降電壓穩壓器

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產品規格表

TPS74201

現行
產品規格表 立即訂購

產品詳細資料

Output options Adjustable Output Iout (max) (A) 1.5 Vin (max) (V) 5.5 Vin (min) (V) 0.8 Vout (max) (V) 3.5 Vout (min) (V) 0.8 Noise (µVrms) 13 Iq (typ) (mA) 3 Thermal resistance θJA (°C/W) 27 Rating Catalog Load capacitance (min) (µF) 0 Regulated outputs (#) 1 Features Enable, Power good, Soft start Accuracy (%) 1 PSRR at 100 KHz (dB) 52 Dropout voltage (Vdo) (typ) (mV) 55 Operating temperature range (°C) -40 to 125
Output options Adjustable Output Iout (max) (A) 1.5 Vin (max) (V) 5.5 Vin (min) (V) 0.8 Vout (max) (V) 3.5 Vout (min) (V) 0.8 Noise (µVrms) 13 Iq (typ) (mA) 3 Thermal resistance θJA (°C/W) 27 Rating Catalog Load capacitance (min) (µF) 0 Regulated outputs (#) 1 Features Enable, Power good, Soft start Accuracy (%) 1 PSRR at 100 KHz (dB) 52 Dropout voltage (Vdo) (typ) (mV) 55 Operating temperature range (°C) -40 to 125
TO-263 (KTW) 7 153.924 mm² 10.1 x 15.24 VQFN (RGR) 20 12.25 mm² 3.5 x 3.5 VQFN (RGW) 20 25 mm² 5 x 5
  • Input Voltage Range: 0.8 V to 5.5 V
  • Soft-Start (SS) Pin Provides a Linear Start-Up With Ramp Time Set by External Capacitor
  • 1% Accuracy Over Line, Load, and Temperature
  • Supports Input Voltages as Low as 0.8 V With External Bias Supply
  • Adjustable Output (0.8 V to 3.6 V)
  • Ultra-Low Dropout: 55 mV at 1.5 A (Typical)
  • Stable With Any or No Output Capacitor
  • Excellent Transient Response
  • Open-Drain Power-Good (VQFN)
  • Active High Enable
  • Input Voltage Range: 0.8 V to 5.5 V
  • Soft-Start (SS) Pin Provides a Linear Start-Up With Ramp Time Set by External Capacitor
  • 1% Accuracy Over Line, Load, and Temperature
  • Supports Input Voltages as Low as 0.8 V With External Bias Supply
  • Adjustable Output (0.8 V to 3.6 V)
  • Ultra-Low Dropout: 55 mV at 1.5 A (Typical)
  • Stable With Any or No Output Capacitor
  • Excellent Transient Response
  • Open-Drain Power-Good (VQFN)
  • Active High Enable

The TPS742 series of low-dropout (LDO) linear regulators provide an easy-to-use, robust power-management solution for a wide variety of applications. User-programmable soft-start minimizes stress on the input power source by reducing capacitive inrush current on start-up. The soft-start is monotonic and well suited for powering many different types of processors and ASICs. The enable input and power-good output allow easy sequencing with external regulators. This complete flexibility permits the user to configure a solution that meets the sequencing requirements of FPGAs, DSPs, and other applications with special start-up requirements.

A precision reference and error amplifier deliver 1% accuracy over load, line, temperature, and process. Each LDO is stable with low-cost ceramic output capacitors, and the family is fully specified from –40°C to 125°C. The TPS742 devices are offered in a small 5-mm × 5-mm VQFN (RGW) and a small 3.5-mm × 3.5-mm VQFN (RGR) package, yielding a highly compact total solution size. For applications that require additional power dissipation, the DDPAK/TO-263 (KTW) package is also available.

The TPS742 series of low-dropout (LDO) linear regulators provide an easy-to-use, robust power-management solution for a wide variety of applications. User-programmable soft-start minimizes stress on the input power source by reducing capacitive inrush current on start-up. The soft-start is monotonic and well suited for powering many different types of processors and ASICs. The enable input and power-good output allow easy sequencing with external regulators. This complete flexibility permits the user to configure a solution that meets the sequencing requirements of FPGAs, DSPs, and other applications with special start-up requirements.

A precision reference and error amplifier deliver 1% accuracy over load, line, temperature, and process. Each LDO is stable with low-cost ceramic output capacitors, and the family is fully specified from –40°C to 125°C. The TPS742 devices are offered in a small 5-mm × 5-mm VQFN (RGW) and a small 3.5-mm × 3.5-mm VQFN (RGR) package, yielding a highly compact total solution size. For applications that require additional power dissipation, the DDPAK/TO-263 (KTW) package is also available.
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TPS74801 現行 具電源良好與啟用功能的 1.5-A、低 VIN (0.8-V) 可調式低壓降 (LDO) 電壓穩壓器 Lower IQ with similar PSRR performance

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類型 標題 日期
* Data sheet TPS742 1.5-A Ultra-LDO With Programmable Soft-Start datasheet (Rev. N) PDF | HTML 2016年 11月 17日
Application note LDO Noise Demystified (Rev. B) PDF | HTML 2020年 8月 18日
Application note Using Thermal Calculation Tools for Analog Components (Rev. A) 2019年 8月 30日
Application note A Topical Index of TI LDO Application Notes (Rev. F) 2019年 6月 27日
Application note LDO PSRR Measurement Simplified (Rev. A) PDF | HTML 2017年 8月 9日
Application note LDO Performance Near Dropout 2010年 10月 8日
Application note Using New Thermal Metrics 2009年 12月 15日
Analog Design Journal Q3 2007 Issue Analog Applications Journal 2007年 8月 10日
Analog Design Journal Simultaneous power-down sequencing with the TPS74x01 family of linear regulators 2007年 8月 10日
Analog Design Journal A 3-A, 1.2-Vout linear regulator with 80% efficiency and Plost < 1W 2006年 10月 10日
EVM User's guide TPS74x01EVM-118 User's Guide 2006年 6月 20日

設計與開發

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模擬型號

TPS74201 PSpice Transient Model (Rev. B)

SLIM016B.ZIP (61 KB) - PSpice Model
下載
模擬型號

TPS74201 TINA-TI Transient Reference Design

SLIM289.TSC (106 KB) - TINA-TI Reference Design
下載
模擬型號

TPS74201 TINA-TI Transient Spice Model

SLIM288.ZIP (36 KB) - TINA-TI Spice Model
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模擬型號

TPS74201 Unencrypted PSpice Transient Model

SBVM620.ZIP (3 KB) - PSpice Model
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電路圖: PDF
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電路圖: PDF
參考設計

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電路圖: PDF
參考設計

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使用指南: PDF
電路圖: PDF
封裝 引腳 下載
TO-263 (KTW) 7 檢視選項
VQFN (RGR) 20 檢視選項
VQFN (RGW) 20 檢視選項
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