SPRS841E March 2012 – October 2019 TMS320C6652 , TMS320C6654
Refer to the PDF data sheet for device specific package drawings
The priority level of all master peripheral traffic is defined at the TeraNet boundary. User programmable priority registers allow software configuration of the data traffic through the TeraNet. A lower number means higher priority - PRI = 000b = urgent, PRI = 111b = low.
Most master ports provide their priority directly and do not need a default priority setting. Examples include the CorePacs, whose priorities are set through software in the UMC control registers. All the packet-DMA-based peripherals also have internal registers to define the priority level of their initiated transactions.
Some masters do not have apriority allocation register of their own. For these masters, a priority allocation register is provided for them and described Section 9.4.1 and Section 9.4.2. For all other modules, see the respective User Guides in Section 10.3 for programmable priority registers.