Refer to the PDF data sheet for device specific package drawings
The C6654 and C6652 devices have seven 64-bit timers in total. Timer0 is dedicated to the CorePac as a watchdog timer and can also be used as a general-purpose timer. Each of the other six timers can also be configured as a general-purpose timer only, programmed as a 64-bit timer or as two separate 32-bit timers.
When operating in 64-bit mode, the timer counts either VBUS clock cycles or input (TINPLx) pulses (rising edge) and generates an output pulse/waveform (TOUTLx) plus an internal event (TINTLx) on a software-programmable period.
When operating in 32-bit mode, the timer is split into two independent 32-bit timers. Each timer is made up of two 32-bit counters: a high counter and a low counter. The timer pins, TINPLx and TOUTLx are connected to the low counter. The timer pins, TINPHx and TOUTHx are connected to the high counter.
When operating in watchdog mode, the timer counts down to 0 and generates an event. It is a requirement that software writes to the timer before the count expires, after which the count begins again. If the count ever reaches 0, the timer event output is asserted. Reset initiated by a watchdog timer can be set by programming Section 18.104.22.168 and the type of reset initiated can set by programming Section 22.214.171.124. For more information, see the 64-bit Timer (Timer 64) for KeyStone Devices User's Guide.