Refer to the PDF data sheet for device specific package drawings
The KeyStone DSP DDR3 Implementation Guidelines specifies a complete DDR3 interface solution as well as a list of compatible DDR3 devices. The DDR3 electrical requirements are fully specified in the DDR3 Jedec Specification JESD79-3C. TI has performed the simulation and system characterization to ensure all DDR3 interface timings in this solution are met; therefore, no electrical data/timing information is supplied here for this interface.
TI supports only designs that follow the board design guidelines outlined in the application report.