Refer to the PDF data sheet for device specific package drawings
Memory protection allows an operating system to define who or what is authorized to access L1D, L1P, and L2 memory. To accomplish this, the L1D, L1P, and L2 memories are divided into pages. There are 16 pages of L1P (2KB each), 16 pages of L1D (2KB each), and 32 pages of L2 (16KB each). The L1D, L1P, and L2 memory controllers in the C66x CorePac are equipped with a set of registers that specify the permissions for each memory page.
Each page may be assigned with fully orthogonal user and supervisor read, write, and execute permissions. In addition, a page may be marked as either (or both) locally accessible or globally accessible. A local access is a direct DSP access to L1D, L1P, and L2, while a global access is initiated by a DMA (either IDMA or the EDMA3) or by other system masters. EDMA or IDMA transfers programmed by the DSP count as global accesses.
The DSP and each of the system masters on the device are all assigned a privilege ID. It is possible to specify whether memory pages are locally or globally accessible.
The AIDx and LOCAL bits of the memory protection page attribute registers specify the memory page protection scheme, see Table 7-1.
|AIDx BIT||LOCAL BIT||DESCRIPTION|
|0||0||No access to memory page is permitted.|
|0||1||Only direct access by DSP is permitted.|
|1||0||Only accesses by system masters and IDMA are permitted (includes EDMA and IDMA accesses initiated by the DSP).|
|1||1||All accesses permitted.|
Faults are handled by software in an interrupt (or an exception, programmable within the C66x CorePac interrupt controller) service routine. A DSP or DMA access to a page without the proper permissions will:
The software is responsible for taking corrective action to respond to the event and resetting the error status in the memory controller. For more information on memory protection for L1D, L1P, and L2, see the C66x CorePac User's Guide.