||See Figure 6-43
||Boot Dev Addr
||The I2C device address to boot from
||Boot Dev Addr Ext
||Extended boot device address, or I2C bus address (typically 0x50, 0x51)
||In master broadcast boot, this is the I2C address to send the boot data to
||The I2C address of this device.
||The operating frequency of the device (MHz). Used to compute the divide down to the I2C module
||The desired I2C data rate (kHz).
||Next Dev Addr
||The next device to boot from (used in boot config mode)
||Next Dev Addr Ext
||The extended next boot device address
||The number of CPU cycles to delay between writing the address to an I2C EEPROM and reading data. This allows the I2C EEPROM time to load the data.