Refer to the PDF data sheet for device specific package drawings
The C66x CorePac in the device contains a 1024KB level-2 memory (L2), a 32KB level-1 program memory (L1P), and a 32KB level-1 data memory (L1D). The C6654 and C6652 devices also contain a 1024KB multicore shared memory (MSM). All memory on the C6654 and C6652 have a unique location in the memory map (see Table 6-60).
After device reset, L1P and L1D cache are configured as all cache, by default. The L1P and L1D cache can be reconfigured through software through the L1PMODE field of the L1P Configuration Register (L1PCFG) and the L1DMODE field of the L1D Configuration Register (L1DCFG) of the C66x CorePac. L1D is a two-way set-associative cache, while L1P is a direct-mapped cache.
The on-chip bootloader changes the reset configuration for L1P and L1D. For more information, see the Bootloader for the C66x DSP User's Guide.
For more information on the operation L1 and L2 caches, see the C66x DSP User's Guide.