Refer to the PDF data sheet for device specific package drawings
Some of the clock inputs are required to be present for the device to initialize correctly, but behavior of many of the clocks is contingent on the state of the boot configuration pins. Table 6-4 describes the clock sequencing and the conditions that affect the clock operation. All clock drivers should be in a high-impedance state until CVDD is at a valid level and that all clock inputs either be active or in a static state with one leg pulled low and the other connected to CVDD.
|DDRCLK||None||Must be present 16 µs before POR transitions high.|
|CORECLK||None||CORECLK used to clock the core PLL. It must be present 16 µs before POR transitions high.|
|PCIECLK (C6654 only)||PCIE will be used as a boot device.||PCIECLK must be present 16 µs before POR transitions high.|
|PCIE will be used after boot.||PCIECLK is used as a source to the PCIE SERDES PLL. It must be present before the PCIE is removed from reset and programmed.|
|PCIE will not be used.||PCIECLK is not used and should be tied to a static state.|