SPRS841E March 2012 – October 2019 TMS320C6652 , TMS320C6654
Refer to the PDF data sheet for device specific package drawings
On the C6654 and C6652, the GPIO peripheral pins GP[15:0] are also used to latch configuration settings. For more detailed information on device/peripheral configuration and the C6654 and C6652 device pin muxing, see Section 8. For more information on GPIO, see the General Purpose Input/Output (GPIO) for KeyStone Devices User's Guide.