SPRS841E March 2012 – October 2019 TMS320C6652 , TMS320C6654
Refer to the PDF data sheet for device specific package drawings
The PLL default settings are determined by the BOOTMODE[12:10] bits. Table 6-90 shows settings for various input clock frequencies.
|BOOTMODE [12:10]||INPUT CLOCK FREQ (MHz)||850 MHz DEVICE|
OUTPUT_DIVIDE is the value of the field of SECCTL[22:19]. This will set the PLL to the maximum clock setting for the device (with OUTPUT_DIVIDE=2, by default).
The Main PLL is controlled using a PLL controller and a chip-level MMR. The DDR3 PLL is controlled by chip level MMRs. For details on how to set up the PLL see Section 6.5. For details on the operation of the PLL controller module, see the Phase-Locked Loop (PLL) for KeyStone Devices User's Guide.