Refer to the PDF data sheet for device specific package drawings
The C6654 and C6652 include one 32-bit-wide 1.5-V DDR3 SDRAM EMIF interface. The DDR3 interface can operate at 800 Mega transfers per second (MTS) and 1033 MTS.
Due to the complicated nature of the interface, a limited number of topologies will be supported to provide a 16-bit or 32-bit interface.
The DDR3 electrical requirements are fully specified in the DDR Jedec Specification JESD79-3C. Standard DDR3 SDRAMs are available in 8- and 16-bit versions, allowing for the following bank topologies to be supported by the interface:
The approach to specifying interface timing for the DDR3 memory bus is different than on other interfaces such as I2C or SPI. For these other interfaces, the device timing was specified in terms of data manual specifications and I/O buffer information specification (IBIS) models. For the DDR3 memory bus, the approach is to specify compatible DDR3 devices and provide the printed circuit board (PCB) solution and guidelines directly to the user.
A race condition may exist when certain masters write data to the DDR3 memory controller. For example, if master A passes a software message through a buffer in external memory and does not wait for an indication that the write completes, before signaling to master B that the message is ready, when master B attempts to read the software message, then the master B read may bypass the master A write and, thus, master B may read stale data and, therefore, receive an incorrect message.
Some master peripherals (for example, EDMA3 transfer controllers with TCCMOD=0) will always wait for the write to complete before signaling an interrupt to the system, thus avoiding this race condition. For masters that do not have a hardware specification of write-read ordering, it may be necessary to specify data ordering through software.
If master A does not wait for indication that a write is complete, it must perform the following workaround: