Refer to the PDF data sheet for device specific package drawings
A hard reset will reset everything on the device except the PLLs, test, emulation logic, and reset isolation modules. POR should also remain deasserted during this time.
Hard reset is initiated by the following:
All the above initiators, by default, are configured to act as a hard reset. Except emulation, all the other three initiators can be configured as soft resets in the RSCFG register in PLLCTL.
The following sequence must be followed during a hard reset:
The POR pin should be held inactive (high) throughout the warm reset sequence. Otherwise, if POR is activated (brought low), the minimum POR pulse width must be met. The RESET pin should not be tied together with the POR pin.