Refer to the PDF data sheet for device specific package drawings
Increasing the device complexity increases its power consumption and with the smaller transistor structures responsible for higher achievable clock rates and increased performance, comes an inevitable penalty, increasing the leakage currents. Leakage currents are present in any active circuit, independently of clock rates and usage scenarios. This static power consumption is mainly determined by transistor type and process technology. Higher clock rates also increase dynamic power, the power used when transistors switch. The dynamic power depends mainly on a specific usage scenario, clock rates, and I/O activity.
TI's SmartReflex technology is used to decrease both static and dynamic power consumption while maintaining the device performance. SmartReflex in the C6654 and C6652 devices is a feature that allows the core voltage to be optimized based on the process corner of the device. This requires a voltage regulator for each device.
To ensure maximizing performance and minimizing power consumption of the device, SmartReflex is required to be implemented whenever the C6654 and C6652 devices are used. The voltage selection is done using four VCNTL pins which are used to select the output voltage of the core voltage regulator.
For information on implementation of SmartReflex see the Power Management for KeyStone Devices application report and the Hardware Design Guide for KeyStone Devices.