8.3.10 Power State Control (PWRSTATECTL) Register
The PWRSTATECTL register is controlled by the software to indicate the power-saving mode. ROM code reads this register to differentiate between the various power saving modes. This register is cleared only by POR and will survive all other device resets. See the Hardware Design Guide for KeyStone Devices for more information. The Power State Control Register is shown in Figure 8-9 and described in Table 8-11.
Figure 8-9 Power State Control Register (PWRSTATECTL)
|RW, +0000 0000 0000 0000 0000 0000 0000 0
|Legend: RW = Read/Write; -n = value after reset
Table 8-11 Power State Control Register (PWRSTATECTL) Field Descriptions
||Used to provide a start address for execution out of the hibernation modes. See the Bootloader for the C66x DSP User's Guide.
||Indicates whether the device is in hibernation mode 1 or mode 2.
- 0 = Hibernation mode 1
- 1 = Hibernation mode 2
||Indicates whether the device is in hibernation mode or not.
- 0 = Not in hibernation mode
- 1 = Hibernation mode
||Indicates whether the device is in standby mode or not.
- 0 = Not in standby mode
- 1 = Standby mode