SPRS841E March 2012 – October 2019 TMS320C6652 , TMS320C6654
Refer to the PDF data sheet for device specific package drawings
The PWRSTATECTL register is controlled by the software to indicate the power-saving mode. ROM code reads this register to differentiate between the various power saving modes. This register is cleared only by POR and will survive all other device resets. See the Hardware Design Guide for KeyStone Devices for more information. The Power State Control Register is shown in Figure 8-9 and described in Table 8-11.
|RW, +0000 0000 0000 0000 0000 0000 0000 0||RW,+0||RW,+0||RW,+0|
|Legend: RW = Read/Write; -n = value after reset|
|31-3||GENERAL_PURPOSE||Used to provide a start address for execution out of the hibernation modes. See the Bootloader for the C66x DSP User's Guide.|
|2||HIBERNATION_MODE||Indicates whether the device is in hibernation mode 1 or mode 2.
|1||HIBERNATION||Indicates whether the device is in hibernation mode or not.
|0||STANDBY||Indicates whether the device is in standby mode or not.