9.4.1 Packet DMA Priority Allocation (PKTDMA_PRI_ALLOC) Register
The packet DMA secondary port is one master port that does not have priority allocation register inside the IP. The priority level for transaction from this master port is described by PKTDMA_PRI_ALLOC register in Figure 9-6 and Table 9-3.
Figure 9-6 Packet DMA Priority Allocation Register (PKTDMA_PRI_ALLOC)
|LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 9-3 Packet DMA Priority Allocation Register (PKTDMA_PRI_ALLOC) Field Descriptions
||Control the priority level for the transactions from packet DMA master port, which access the external linking RAM.