Refer to the PDF data sheet for device specific package drawings
In master mode, the I2C device configuration uses 10 bits of device configuration instead of 7 as used in other boot modes. In this mode, the device will make the initial read of the I2C EEPROM while the PLL is in bypass mode. The initial read will contain the desired clock multiplier, which will be set up prior to any subsequent reads. I2C master mode is shown in Figure 6-34 and described in Table 6-70.
|12||Mode||I2C operation mode
|11 - 10||Address||I2C bus address configuration
|9||Speed||I2C data rate configuration
|8-3||Parameter Index||Identifies the index of the configuration table initially read from the I2C EEPROM
This value can range from 0 to 63.