Refer to the PDF data sheet for device specific package drawings
IPCARx are the IPC interrupt-acknowledgement registers to facilitate inter-CorePac core interrupts.
The C6654 and C6652 have only IPCAR0. This register also provides a Source ID facility by which up to 28 different sources of interrupts can be identified. Allocation of source bits to source processor and meaning is entirely based on software convention. The register field descriptions are shown in the following tables. Virtually anything can be a source for these registers as this is completely controlled by software. Any master that has access to BOOTCFG module space can write to these registers. The IPC Acknowledgement Register is shown in Figure 8-12 and described in Table 8-14.
|SRCC23 – SRCC4||SRCC3||SRCC2||SRCC1||SRCC0||Reserved|
|RW +0||RW +0||RW +0||RW +0||RW +0 (per bit field)||RW +0||RW +0||RW +0||RW +0||R, +0000|
|Legend: R = Read only; RW = Read/Write; -n = value after reset|
|31-4||SRCCx||Interrupt source acknowledgement.
Reads return current value of internal register bit.