Refer to the PDF data sheet for device specific package drawings
The IPCGRH register facilitates interrupts to external hosts. Operation and use of the IPCGRH register is the same as for other IPCGR registers. The interrupt output pulse created by the IPCGRH register appears on device pin HOUT.
The host interrupt output pulse should be stretched. It should be asserted for 4 bootcfg clock cycles (CPU/6) followed by a deassertion of 4 bootcfg clock cycles. Generating the pulse will result in 8 CPU/6 cycle pulse blocking window. Write to IPCGRH with IPCG bit (bit 0) set will only generate a pulse if they are beyond 8 CPU/6 cycle period. The IPC Generation Host Register is shown in Figure 8-13 and described in Table 8-15.
|SRCS23 – SRCS4||SRCS3||SRCS2||SRCS1||SRCS0||Reserved||IPCG|
|RW +0||RW +0||RW +0||RW +0||RW +0 (per bit field)||RW +0||RW +0||RW +0||RW +0||R, +000||RW +0|
|Legend: R = Read only; RW = Read/Write; -n = value after reset|
|31-4||SRCSx||Interrupt source indication.
Reads return current value of internal register bit.
|0||IPCG||Host interrupt generation.
Reads return 0.