Refer to the PDF data sheet for device specific package drawings
IPCGRx are the IPC interrupt generation registers to facilitate inter CorePac interrupts.
The C6654 and C6652 have only IPCGR0. This register can be used by external hosts to generate interrupts to the CorePac. A write of 1 to the IPCG field of the IPCGRx register will generate an interrupt pulse to the CorePac.
This register also provides a Source ID facility by which up to 28 different sources of interrupts can be identified. Allocation of source bits to source processor and meaning is entirely based on software convention. The register field descriptions are given in the following tables. Virtually anything can be a source for these registers as this is completely controlled by software. Any master that has access to BOOTCFG module space can write to these registers. The IPC Generation Register is shown in Figure 8-11 and described in Table 8-13.
|SRCS23 – SRCS4||SRCS3||SRCS2||SRCS1||SRCS0||Reserved||IPCG|
|RW +0||RW +0||RW +0||RW +0||RW +0 (per bit field)||RW +0||RW +0||RW +0||RW +0||R, +000||RW +0|
|Legend: R = Read only; RW = Read/Write; -n = value after reset|
|31-4||SRCSx||Interrupt source indication.
Reads return current value of internal register bit.
|0||IPCG||Inter-DSP interrupt generation.
Reads return 0.