SWCU194 March 2023 CC1314R10 , CC1354P10 , CC1354R10 , CC2674P10 , CC2674R10
Table 2-171 lists the memory-mapped registers for the CPU_DCB registers. All register offset addresses not listed in Table 2-171 should be considered as reserved locations and the register contents should not be modified.
Offset | Acronym | Register Name | Section |
---|---|---|---|
10h | DHCSR | Controls halting debug | Section 2.5.8.1 |
14h | DCRSR | With the DCRDR, provides debug access to the general-purpose registers, special-purpose registers, and the FP extension registers. A write to the DCRSR specifies the register to transfer, whether the transfer is a read or write, and starts the transfer | Section 2.5.8.2 |
18h | DCRDR | With the DCRSR, provides debug access to the general-purpose registers, special-purpose registers, and the FP Extension registers. If the Main Extension is implemented, it can also be used for message passing between an external debugger and a debug agent running on the PE | Section 2.5.8.3 |
1Ch | DEMCR | Manages vector catch behavior and DebugMonitor handling when debugging | Section 2.5.8.4 |
24h | DAUTHCTRL | This register allows the external authentication interface to be | Section 2.5.8.5 |
28h | DSCSR | Provides control and status information for Secure debug | Section 2.5.8.6 |
Complex bit access types are encoded to fit into small table cells. Table 2-172 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
Write Type | ||
W | W | Write |
Reset or Default Value | ||
-n | Value after reset or the default value |
DHCSR is shown in Table 2-173.
Return to the Summary Table.
Controls halting debug
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-27 | RESERVED | R | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
26 | S_RESTART_ST | R | 0h | Indicates the PE has processed a request to clear DHCSR.C_HALT to 0. That is, either a write to DHCSR that clears DHCSR.C_HALT from 1 to 0, or an External Restart Request |
25 | S_RESET_ST | R | 0h | Indicates whether the PE has been reset since the last read of the DHCSR |
24 | S_RETIRE_ST | R | 0h | Set to 1 every time the PE retires one of more instructions |
23-21 | RESERVED | R | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
20 | S_SDE | R | 0h | Indicates whether Secure invasive debug is allowed |
19 | S_LOCKUP | R | 0h | Indicates whether the PE is in Lockup state |
18 | S_SLEEP | R | 0h | Indicates whether the PE is sleeping |
17 | S_HALT | R | 0h | Indicates whether the PE is in Debug state |
31-16 | DBGKEY | W | 0h | A debugger must write 0xA05F to this field to enable write access to the remaining bits, otherwise the PE ignores the write access |
15-6 | RESERVED | R | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
5 | C_SNAPSTALL | R | 0h | Allow imprecise entry to Debug state |
4 | RESERVED | R | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
3 | C_MASKINTS | R/W | 0h | When debug is enabled, the debugger can write to this bit to mask PendSV, SysTick and external configurable interrupts |
2 | C_STEP | R/W | 0h | Enable single instruction step |
1 | C_HALT | R/W | 0h | PE enter Debug state halt request |
0 | C_DEBUGEN | R/W | 0h | Enable Halting debug |
DCRSR is shown in Table 2-174.
Return to the Summary Table.
With the DCRDR, provides debug access to the general-purpose registers, special-purpose registers, and the FP extension registers. A write to the DCRSR specifies the register to transfer, whether the transfer is a read or write, and starts the transfer
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-17 | RESERVED | R | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
16 | REGWnR | W | 0h | Specifies the access type for the transfer |
15-7 | RESERVED | R | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
6-0 | REGSEL | W | 0h | Specifies the general-purpose register, special-purpose register, or FP register to transfer |
DCRDR is shown in Table 2-175.
Return to the Summary Table.
With the DCRSR, provides debug access to the general-purpose registers, special-purpose registers, and the FP Extension registers. If the Main Extension is implemented, it can also be used for message passing between an external debugger and a debug agent running on the PE
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | DBGTMP | R/W | 0h | Provides debug access for reading and writing the general-purpose registers, special-purpose registers, and Floating-point Extension registers |
DEMCR is shown in Table 2-176.
Return to the Summary Table.
Manages vector catch behavior and DebugMonitor handling when debugging
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-25 | RESERVED | R | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
24 | TRCENA | R/W | 0h | Global enable for all DWT and ITM features |
23-21 | RESERVED | R | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
20 | SDME | R | 0h | Indicates whether the DebugMonitor targets the Secure or the Non-secure state and whether debug events are allowed in Secure state |
19 | MON_REQ | R | 0h | DebugMonitor semaphore bit |
18 | MON_STEP | R | 0h | Enable DebugMonitor stepping |
17 | MON_PEND | R | 0h | Sets or clears the pending state of the DebugMonitor exception |
16 | MON_EN | R | 0h | Enable the DebugMonitor exception |
15-12 | RESERVED | R | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
11 | VC_SFERR | R | 0h | SecureFault exception halting debug vector catch enable |
10 | VC_HARDERR | R/W | 0h | HardFault exception halting debug vector catch enable |
9 | VC_INTERR | R | 0h | Enable halting debug vector catch for faults during exception entry and return |
8 | VC_BUSERR | R | 0h | BusFault exception halting debug vector catch enable |
7 | VC_STATERR | R | 0h | Enable halting debug trap on a UsageFault exception caused by a state information error, for example an Undefined Instruction exception |
6 | VC_CHKERR | R | 0h | Enable halting debug trap on a UsageFault exception caused by a checking error, for example an alignment check error |
5 | VC_NOCPERR | R | 0h | Enable halting debug trap on a UsageFault caused by an access to a coprocessor |
4 | VC_MMERR | R | 0h | Enable halting debug trap on a MemManage exception |
3-1 | RESERVED | R | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
0 | VC_CORERESET | R/W | 0h | Enable Reset Vector Catch. This causes a warm reset to halt a running system |
DAUTHCTRL is shown in Table 2-177.
Return to the Summary Table.
This register allows the external authentication interface to be
overridden from software.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
3 | INTSPNIDEN | R/W | 0h | Internal Secure non-invasive debug enable. Overrides the external Secure non-invasive debug authentication interface |
2 | SPNIDENSEL | R/W | 0h | Secure non-invasive debug enable select. Selects between DAUTHCTRL and the external authentication interface for control of Secure non-invasive debug |
1 | INTSPIDEN | R/W | 0h | Internal Secure invasive debug enable. Overrides the external Secure invasive debug authentication Interfaces. |
0 | SPIDENSEL | R/W | 0h | Secure invasive debug enable select. Selects between DAUTHCTRL and the external authentication interface for control of Secure invasive debug. |
DSCSR is shown in Table 2-178.
Return to the Summary Table.
Provides control and status information for Secure debug
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-18 | RESERVED | R | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
17 | CDSKEY | R/W | 0h | Writes to the CDS bit are ignored unless CDSKEY is concurrently written to zero |
16 | CDS | R/W | 0h | This field indicates the current Security state of the processor |
15-2 | RESERVED | R | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
1 | SBRSEL | R/W | 0h | If SBRSELEN is 1 this bit selects whether the Non-secure or the Secure version of the memory-mapped Banked registers are accessible to the debugger |
0 | SBRSELEN | R/W | 0h | Controls whether the SBRSEL field or the current Security state of the processor selects which version of the memory-mapped Banked registers are accessed to the debugger |