SWCU194 March 2023 CC1314R10 , CC1354P10 , CC1354R10 , CC2674P10 , CC2674R10
The debug subsystem has only one slave DAP (CPU DAP). This debug port implements Cortex®- DAP interface, which allows external access to an Advanced High-performance Bus Access Port (AHB-AP) interface for debug accesses in the CPU.
The Cortex®- DAP is a standard Arm® CoreSight™ debug port that can be configured as JTAG Debug Port (JTAG-DP), Serial Wire Debug Port (SW-DP) or Serial Wire/JTAG Debug Port (SWJ-DP). Even though the SW-DP interface is supported by SWJ-DP, the CC13x4x10 and CC26x4x10 device platform does not use this mode. The Cortex®- DAP is configured to work in JTAG-DP mode only. The key reason is that SW-DP becomes redundant for the design in the presence of the 2-pin JTAG (1149.7) mode.