SWCU194 March   2023 CC1314R10 , CC1354P10 , CC1354R10 , CC2674P10 , CC2674R10

 

  1.   Read This First
    1.     About This Manual
    2.     Devices
    3.     Register, Field, and Bit Calls
    4.     Related Documentation
    5.     Trademarks
  2. 1 Architectural Overview
    1. 1.1 Target Applications
    2. 1.2 Overview
    3. 1.3 Functional Overview
      1. 1.3.1  ArmCortex-M33 with FPU
        1. 1.3.1.1 Processor Core
        2. 1.3.1.2 System Timer (SysTick)
        3. 1.3.1.3 Nested Vector Interrupt Controller (NVIC)
        4. 1.3.1.4 System Control Block (SCB)
      2. 1.3.2  On-Chip Memory
        1. 1.3.2.1 SRAM
        2. 1.3.2.2 Flash Memory
        3. 1.3.2.3 ROM
      3. 1.3.3  Radio
      4. 1.3.4  Security Core
      5. 1.3.5  Runtime Security
      6. 1.3.6  General-Purpose Timers
        1. 1.3.6.1 Watchdog Timer
        2. 1.3.6.2 Always-On Domain
      7. 1.3.7  Direct Memory Access
      8. 1.3.8  System Control and Clock
      9. 1.3.9  Serial Communication Peripherals
        1. 1.3.9.1 UART
        2. 1.3.9.2 I2C
        3. 1.3.9.3 I2S
        4. 1.3.9.4 SPI
      10. 1.3.10 Programmable I/Os
      11. 1.3.11 Sensor Controller
      12. 1.3.12 Random Number Generator
      13. 1.3.13 cJTAG and JTAG
      14. 1.3.14 Power Supply System
        1. 1.3.14.1 Supply System
          1. 1.3.14.1.1 VDDS
          2. 1.3.14.1.2 VDDR
          3. 1.3.14.1.3 Digital Core Supply
          4. 1.3.14.1.4 Other Internal Supplies
        2. 1.3.14.2 DC/DC Converter
  3. 2  Arm Cortex-M33 Processor with FPU
    1. 2.1 Arm Cortex-M33 Processor Introduction
    2. 2.2 Block Diagram
    3. 2.3 Overview
      1. 2.3.1 Integrated Configurable Debug
      2. 2.3.2 Trace Port Interface Unit
      3. 2.3.3 Arm Cortex-M33 System Peripheral Details
        1. 2.3.3.1 Floating Point Unit (FPU)
        2. 2.3.3.2 Memory Protection Unit (MPU)
        3. 2.3.3.3 System Timer (SysTick)
        4. 2.3.3.4 Nested Vectored Interrupt Controller (NVIC)
        5. 2.3.3.5 System Control Block (SCB)
        6. 2.3.3.6 System Control Space (SCS)
        7. 2.3.3.7 Security Attribution Unit (SAU)
    4. 2.4 Programming Model
      1. 2.4.1 Modes of Operation and Execution
        1. 2.4.1.1 Security States
        2. 2.4.1.2 Operating Modes
        3. 2.4.1.3 Operating States
        4. 2.4.1.4 Privileged Access and Unprivileged User Access
      2. 2.4.2 Instruction Set Summary
      3. 2.4.3 Memory Model
        1. 2.4.3.1 Private Peripheral Bus
        2. 2.4.3.2 Unaligned Accesses
      4. 2.4.4 Exclusive Monitor
      5. 2.4.5 Processor Core Registers Summary
      6. 2.4.6 Exceptions
        1. 2.4.6.1 Exception Handling and Prioritization
      7. 2.4.7 Runtime Security
        1. 2.4.7.1 IDAU Watermark Registers
        2. 2.4.7.2 Secure Memory Range for Registers
        3. 2.4.7.3 Bus Topology
        4. 2.4.7.4 Intended Use
    5. 2.5 Arm® Cortex®-M33 Registers
      1. 2.5.1  CPU_ITM Registers
      2. 2.5.2  CPU_DWT Registers
      3. 2.5.3  CPU_SYSTICK Registers
      4. 2.5.4  CPU_NVIC Registers
      5. 2.5.5  CPU_SCS Registers
      6. 2.5.6  CPU_MPU Registers
      7. 2.5.7  CPU_SAU Registers
      8. 2.5.8  CPU_DCB Registers
      9. 2.5.9  CPU_SIG Registers
      10. 2.5.10 CPU_FPU Registers
      11. 2.5.11 CPU_TPIU Registers
  4. 3 Memory Map
    1. 3.1 Introduction
    2. 3.2 Memory Map (Secure and Non-secure)
      1. 3.2.1 Bus Security
    3. 3.3 Memory Map
  5. 4  Arm Cortex-M33 Peripherals
    1. 4.1 Arm Cortex-M33 Peripherals Introduction
  6. 5 Interrupts and Events
    1. 5.1 Exception Model
      1. 5.1.1 Exception States
      2. 5.1.2 Exception Types
      3. 5.1.3 Exception Handlers
      4. 5.1.4 Vector Table
      5. 5.1.5 Exception Priorities
      6. 5.1.6 Interrupt Priority Grouping
      7. 5.1.7 Exception Entry and Return
        1. 5.1.7.1 Exception Entry
        2. 5.1.7.2 Exception Return
    2. 5.2 Fault Handling
      1. 5.2.1 Fault Types
      2. 5.2.2 Fault Escalation and Hard Faults
      3. 5.2.3 Fault Status Registers and Fault Address Registers
      4. 5.2.4 Lockup
    3. 5.3 Security State Switches
    4. 5.4 Event Fabric
      1. 5.4.1 Introduction
      2. 5.4.2 Event Fabric Overview
        1. 5.4.2.1 Registers
    5. 5.5 AON Event Fabric
      1. 5.5.1 Common Input Event List
      2. 5.5.2 Event Subscribers
        1. 5.5.2.1 AON Power Management Controller (AON_PMCTL)
        2. 5.5.2.2 Real-Time Clock
        3. 5.5.2.3 MCU Event Fabric
    6. 5.6 MCU Event Fabric
      1. 5.6.1 Common Input Event List
      2. 5.6.2 Event Subscribers
        1. 5.6.2.1 System CPU
        2. 5.6.2.2 NMI
        3. 5.6.2.3 Freeze
    7. 5.7 AON Events
    8. 5.8 Interrupts and Events Registers
      1. 5.8.1 AON_EVENT Registers
      2. 5.8.2 EVENT Registers
  7. 6 JTAG Interface
    1. 6.1 Overview
    2. 6.2 cJTAG
    3. 6.3 ICEPick
      1. 6.3.1 Secondary TAPs
        1. 6.3.1.1 Slave DAP (CPU DAP)
      2. 6.3.2 ICEPick Registers
        1. 6.3.2.1 IR Instructions
        2. 6.3.2.2 Data Shift Register
        3. 6.3.2.3 Instruction Register
        4. 6.3.2.4 Bypass Register
        5. 6.3.2.5 Device Identification Register
        6. 6.3.2.6 User Code Register
        7. 6.3.2.7 ICEPick Identification Register
        8. 6.3.2.8 Connect Register
      3. 6.3.3 Router Scan Chain
      4. 6.3.4 TAP Routing Registers
        1. 6.3.4.1 ICEPick Control Block
          1. 6.3.4.1.1 All0s Register
          2. 6.3.4.1.2 ICEPick Control Register
          3. 6.3.4.1.3 Linking Mode Register
        2. 6.3.4.2 Test TAP Linking Block
          1. 6.3.4.2.1 Secondary Test TAP Register
        3. 6.3.4.3 Debug TAP Linking Block
          1. 6.3.4.3.1 Secondary Debug TAP Register
    4. 6.4 ICEMelter
    5. 6.5 Serial Wire Viewer (SWV)
    6. 6.6 Halt In Boot (HIB)
    7. 6.7 Debug and Shutdown
    8. 6.8 Boundary Scan
  8. 7 Power, Reset, and Clock Management (PRCM)
    1. 7.1 Introduction
    2. 7.2 System CPU Mode
    3. 7.3 Supply System
      1. 7.3.1 Internal DC/DC Converter and Global LDO
      2. 7.3.2 External Regulator Mode
    4. 7.4 Digital Power Partitioning
      1. 7.4.1 MCU_VD
        1. 7.4.1.1 MCU_VD Power Domains
      2. 7.4.2 AON_VD
        1. 7.4.2.1 AON_VD Power Domains
    5. 7.5 Clock Management
      1. 7.5.1 System Clocks
        1. 7.5.1.1 Controlling the Oscillators
      2. 7.5.2 Clocks in MCU_VD
        1. 7.5.2.1 Clock Gating
        2. 7.5.2.2 Scaler to GPTs
        3. 7.5.2.3 Scaler to WDT
      3. 7.5.3 Clocks in AON_VD
    6. 7.6 Power Modes
      1. 7.6.1 Start-Up State
      2. 7.6.2 Active Mode
      3. 7.6.3 Idle Mode
      4. 7.6.4 Standby Mode
      5. 7.6.5 Shutdown Mode
    7. 7.7 Reset
      1. 7.7.1 System Resets
        1. 7.7.1.1 Clock Loss Detection
        2. 7.7.1.2 Software-Initiated System Reset
        3. 7.7.1.3 Warm Reset Converted to System Reset
      2. 7.7.2 Reset of the MCU_VD Power Domains and Modules
      3. 7.7.3 Reset of AON_VD
      4. 7.7.4 Always On Watchdog Timer (AON_WDT)
    8. 7.8 PRCM Registers
      1. 7.8.1 PRCM Registers
      2. 7.8.2 AON_PMCTL Registers
      3. 7.8.3 DDI_0_OSC Registers
  9. 8 Versatile Instruction Memory System (VIMS)
    1. 8.1 Introduction
    2. 8.2 VIMS Configurations
      1. 8.2.1 VIMS Modes
        1. 8.2.1.1 GPRAM Mode
        2. 8.2.1.2 Off Mode
        3. 8.2.1.3 Cache Mode
      2. 8.2.2 VIMS FLASH Line Buffers
      3. 8.2.3 VIMS Arbitration
      4. 8.2.4 VIMS Cache TAG Prefetch
    3. 8.3 VIMS Software Remarks
      1. 8.3.1 FLASH Program or Update
      2. 8.3.2 VIMS Retention
        1. 8.3.2.1 Mode 1
        2. 8.3.2.2 Mode 2
        3. 8.3.2.3 Mode 3
    4. 8.4 FLASH
      1. 8.4.1 Flash Memory Protection
      2. 8.4.2 Flash Memory Programming
    5. 8.5 ROM Functions
    6. 8.6 VIMS Registers
      1. 8.6.1 FLASH Registers
      2. 8.6.2 VIMS Registers
      3. 8.6.3 NVMNW Registers
  10. 9 SRAM
    1. 9.1 Introduction
    2. 9.2 Main Features
    3. 9.3 Data Retention
    4. 9.4 Parity and SRAM Error Support
      1. 9.4.1 SRAM Extension Mode
    5. 9.5 SRAM Auto-Initialization
    6. 9.6 Parity Debug Behavior
    7. 9.7 SRAM Registers
      1. 9.7.1 SRAM_MMR Registers
      2. 9.7.2 SRAM Registers
  11. 10Bootloader
    1. 10.1 Bootloader Functionality
      1. 10.1.1 Bootloader Disabling
      2. 10.1.2 Bootloader Backdoor
    2. 10.2 Bootloader Interfaces
      1. 10.2.1 Packet Handling
        1. 10.2.1.1 Packet Acknowledge and Not-Acknowledge Bytes
      2. 10.2.2 Transport Layer
        1. 10.2.2.1 UART Transport
          1. 10.2.2.1.1 UART Baud Rate Automatic Detection
        2. 10.2.2.2 SPI Transport
      3. 10.2.3 Serial Bus Commands
        1. 10.2.3.1  COMMAND_PING
        2. 10.2.3.2  COMMAND_DOWNLOAD
        3. 10.2.3.3  COMMAND_GET_STATUS
        4. 10.2.3.4  COMMAND_SEND_DATA
        5. 10.2.3.5  COMMAND_RESET
        6. 10.2.3.6  COMMAND_SECTOR_ERASE
        7. 10.2.3.7  COMMAND_CRC32
        8. 10.2.3.8  COMMAND_GET_CHIP_ID
        9. 10.2.3.9  COMMAND_MEMORY_READ
        10. 10.2.3.10 COMMAND_MEMORY_WRITE
        11. 10.2.3.11 COMMAND_BANK_ERASE
        12. 10.2.3.12 COMMAND_SET_CCFG
        13. 10.2.3.13 COMMAND_DOWNLOAD_CRC
  12. 11Device Configuration
    1. 11.1 Customer Configuration (CCFG)
      1. 11.1.1 CCFG Recommendations for Final Production
    2. 11.2 CCFG Registers
    3. 11.3 Factory Configuration (FCFG)
    4. 11.4 FCFG1 Registers
  13. 12AES and Hash Cryptoprocessor
    1. 12.1 Introduction
    2. 12.2 Functional Description
      1. 12.2.1 Debug Capabilities
      2. 12.2.2 Exception Handling
      3. 12.2.3 Power Management and Sleep Modes
      4. 12.2.4 Interrupts
      5. 12.2.5 Module Memory Map
      6. 12.2.6 Master Control and Select Module
        1. 12.2.6.1 Algorithm Select Register
          1. 12.2.6.1.1 Algorithm Select
        2. 12.2.6.2 Master PROT Enable
          1. 12.2.6.2.1 Master PROT-Privileged Access-Enable
        3. 12.2.6.3 Software Reset
      7. 12.2.7 AES Engine
        1. 12.2.7.1 Second and Third Key Registers (Internal, but Clearable)
        2. 12.2.7.2 AES Initialization Vector (IV) Registers
        3. 12.2.7.3 AES I/O Buffer Control, Mode, and Length Registers
        4. 12.2.7.4 AES Data Input and Output Registers
        5. 12.2.7.5 TAG Registers
      8. 12.2.8 Key Area Registers
        1. 12.2.8.1 Key Store Write Area Register
        2. 12.2.8.2 Key Store Written Area Register
        3. 12.2.8.3 Key Store Size Register
        4. 12.2.8.4 Key Store Read Area Register
      9. 12.2.9 Hash Engine
        1. 12.2.9.1 Hash I/O Buffer Control and Status Register, Mode, and Length Registers
        2. 12.2.9.2 Hash Data Input and Digest Registers
    3. 12.3 DMA Controller
      1. 12.3.1 Internal Operation
      2. 12.3.2 Supported DMA Operations
    4. 12.4 AES and Hash Cryptoprocessor Performance
      1. 12.4.1 Introduction
      2. 12.4.2 Performance for DMA-Based Operations
    5. 12.5 Programming Guidelines
      1. 12.5.1 One-Time Initialization After a Reset
      2. 12.5.2 DMAC and Master Control
        1. 12.5.2.1 Regular Use
        2. 12.5.2.2 Interrupting DMA Transfers
        3. 12.5.2.3 Interrupts, Hardware, and Software Synchronization
      3. 12.5.3 Hashing
        1. 12.5.3.1 Data Format and Byte Order
        2. 12.5.3.2 Basic Hash with Data From DMA
          1. 12.5.3.2.1 New Hash Session with Digest Read Through Slave
          2. 12.5.3.2.2 New Hash Session with Digest to External Memory
          3. 12.5.3.2.3 Resumed Hash Session
        3. 12.5.3.3 HMAC
          1. 12.5.3.3.1 Secure HMAC
        4. 12.5.3.4 Alternative Basic Hash Where Data Originates from Slave Interface
          1. 12.5.3.4.1 New Hash Session
          2. 12.5.3.4.2 Resumed Hash Session
      4. 12.5.4 Encryption and Decryption
        1. 12.5.4.1 Data Format and Byte Order
        2. 12.5.4.2 Key Store
          1. 12.5.4.2.1 Load Keys from External Memory
        3. 12.5.4.3 Basic AES Modes
          1. 12.5.4.3.1 AES-ECB
          2. 12.5.4.3.2 AES-CBC
          3. 12.5.4.3.3 AES-CTR
          4. 12.5.4.3.4 Programming Sequence with DMA Data
        4. 12.5.4.4 CBC-MAC
          1. 12.5.4.4.1 Programming Sequence for Regular CBC-MAC
          2. 12.5.4.4.2 Programming Sequence for Regular CBC-MAC with Continuation
          3. 12.5.4.4.3 Programming Sequence for CMAC CBC-MAC
          4. 12.5.4.4.4 Programming Sequence for CMAC CBC-MAC with Continuation
        5. 12.5.4.5 AES-CCM
          1. 12.5.4.5.1 Continued CCM Processing
          2. 12.5.4.5.2 Programming Sequence for AES-CCM
          3. 12.5.4.5.3 Programming Sequence for Continued AES-CCM in the AAD Phase
          4. 12.5.4.5.4 Programming Sequence for Continued AES-CCM in the Payload Phase
        6. 12.5.4.6 AES-GCM
          1. 12.5.4.6.1 Continued AES-GCM Processing
          2. 12.5.4.6.2 Programming Sequence for AES-GCM
          3. 12.5.4.6.3 Programming Sequence for Continued AES-GCM in the AAD Phase
          4. 12.5.4.6.4 Programming Sequence for Continued AES-GCM in the Payload Phase
      5. 12.5.5 Exceptions Handling
        1. 12.5.5.1 Soft Reset
        2. 12.5.5.2 External Port Errors
        3. 12.5.5.3 Key Store Errors
    6. 12.6 Conventions and Compliances
      1. 12.6.1 Conventions Used in This Manual
        1. 12.6.1.1 Terminology
        2. 12.6.1.2 Formulas and Nomenclature
      2. 12.6.2 Compliance
    7. 12.7 CRYPTO Registers
  14. 13PKA Engine
    1. 13.1 Introduction
    2. 13.2 Functional Description
      1. 13.2.1 Module Architecture
      2. 13.2.2 PKA RAM
      3. 13.2.3 PKCP Operations
      4. 13.2.4 Sequencer Operations
        1. 13.2.4.1 Modular Exponentiation Operations
        2. 13.2.4.2 Modular Inversion Operation
        3. 13.2.4.3 ECC Operations
      5. 13.2.5 Operation Sequence
    3. 13.3 PKA Engine Performance
      1. 13.3.1 Basic Operations Performance
      2. 13.3.2 ExpMod Performance
      3. 13.3.3 Modular Inversion Performance
      4. 13.3.4 ECC Operation Performance
    4. 13.4 PKA Registers
  15. 14True Random Number Generator (TRNG)
    1. 14.1 Introduction
    2. 14.2 Block Diagram
    3. 14.3 TRNG Software Reset
    4. 14.4 Interrupt Requests
    5. 14.5 TRNG Operation Description
      1. 14.5.1 TRNG Shutdown
      2. 14.5.2 TRNG Alarms
      3. 14.5.3 TRNG Entropy
    6. 14.6 TRNG Low-Level Programming Guide
      1. 14.6.1 Initialization
        1. 14.6.1.1 Interfacing Modules
        2. 14.6.1.2 TRNG Main Sequence
        3. 14.6.1.3 TRNG Operating Modes
          1. 14.6.1.3.1 Polling Mode
          2. 14.6.1.3.2 Interrupt Mode
    7. 14.7 TRNG Registers
  16. 15I/O Controller (IOC)
    1. 15.1  Introduction
    2. 15.2  IOC Overview
    3. 15.3  I/O Mapping and Configuration
      1. 15.3.1 Basic I/O Mapping
      2. 15.3.2 Mapping AUXIOs to DIO Pins
      3. 15.3.3 Control External LNA/PA (Range Extender) with I/Os
      4. 15.3.4 Map the 32 kHz System Clock (SCLK_LF Clock) to DIO
    4. 15.4  Edge Detection on DIO Pins
      1. 15.4.1 Configure DIO as GPIO Input to Generate Interrupt on Edge Detect
    5. 15.5  Unused I/O Pins
    6. 15.6  GPIO
    7. 15.7  I/O Pin Capability
    8. 15.8  Peripheral PORT_IDs
    9. 15.9  I/O Pins
      1. 15.9.1 Input/Output Modes
        1. 15.9.1.1 Physical Pin
        2. 15.9.1.2 Pin Configuration
    10. 15.10 IOC Registers
      1. 15.10.1 AON_IOC Registers
      2. 15.10.2 GPIO Registers
      3. 15.10.3 IOC Registers
  17. 16Micro Direct Memory Access (µDMA)
    1. 16.1 Introduction
    2. 16.2 Block Diagram
    3. 16.3 Functional Description
      1. 16.3.1  Channel Assignments
      2. 16.3.2  Priority
      3. 16.3.3  Arbitration Size
      4. 16.3.4  Request Types
        1. 16.3.4.1 Single Request
        2. 16.3.4.2 Burst Request
      5. 16.3.5  Channel Configuration
      6. 16.3.6  Transfer Modes
        1. 16.3.6.1 Stop Mode
        2. 16.3.6.2 Basic Mode
        3. 16.3.6.3 Auto Mode
        4. 16.3.6.4 Ping-Pong Mode
        5. 16.3.6.5 Memory Scatter-Gather Mode
        6. 16.3.6.6 Peripheral Scatter-Gather Mode
      7. 16.3.7  Transfer Size and Increments
      8. 16.3.8  Peripheral Interface
      9. 16.3.9  Software Request
      10. 16.3.10 Interrupts and Errors
    4. 16.4 Initialization and Configuration
      1. 16.4.1 Module Initialization
      2. 16.4.2 Configuring a Memory-to-Memory Transfer
        1. 16.4.2.1 Configure the Channel Attributes
        2. 16.4.2.2 Configure the Channel Control Structure
        3. 16.4.2.3 Start the Transfer
    5. 16.5 UDMA Registers
  18. 17Timers
    1. 17.1 Introduction
    2. 17.2 Block Diagram
    3. 17.3 Functional Description
      1. 17.3.1 GPTM Reset Conditions
      2. 17.3.2 Timer Modes
        1. 17.3.2.1 One-Shot or Periodic Timer Mode
        2. 17.3.2.2 Input Edge-Count Mode
        3. 17.3.2.3 Input Edge-Time Mode
        4. 17.3.2.4 PWM Mode
        5. 17.3.2.5 Wait-for-Trigger Mode
      3. 17.3.3 Synchronizing GPT Blocks
      4. 17.3.4 Accessing Concatenated 16- and 32-Bit GPTM Register Values
    4. 17.4 Initialization and Configuration
      1. 17.4.1 One-Shot and Periodic Timer Modes
      2. 17.4.2 Input Edge-Count Mode
      3. 17.4.3 Input Edge-Timing Mode
      4. 17.4.4 PWM Mode
      5. 17.4.5 Producing DMA Trigger Events
    5. 17.5 GPT Registers
  19. 18Real-Time Clock (RTC)
    1. 18.1 Introduction
    2. 18.2 Functional Specifications
      1. 18.2.1 Functional Overview
      2. 18.2.2 Free-Running Counter
      3. 18.2.3 Channels
        1. 18.2.3.1 Capture and Compare
      4. 18.2.4 Events
    3. 18.3 RTC Register Information
      1. 18.3.1 Register Access
      2. 18.3.2 Entering Sleep and Wakeup From Sleep
      3. 18.3.3 AON_RTC:SYNC Register
    4. 18.4 RTC Registers
      1. 18.4.1 AON_RTC Registers
  20. 19Watchdog Timer (WDT)
    1. 19.1 Introduction
    2. 19.2 Functional Description
    3. 19.3 Initialization and Configuration
    4. 19.4 WDT Registers
  21. 20AUX Domain Sensor Controller and Peripherals
    1. 20.1 Introduction
      1. 20.1.1 AUX Block Diagram
    2. 20.2 Power and Clock Management
      1. 20.2.1 Operational Modes
        1. 20.2.1.1 Dual-Rate AUX Clock
      2. 20.2.2 Use Scenarios
        1. 20.2.2.1 MCU
        2. 20.2.2.2 Sensor Controller
      3. 20.2.3 SCE Clock Emulation
      4. 20.2.4 AUX RAM Retention
    3. 20.3 Sensor Controller
      1. 20.3.1 Sensor Controller Studio
        1. 20.3.1.1 Programming Model
        2. 20.3.1.2 Task Development
        3. 20.3.1.3 Task Testing, Task Debugging and Run-Time Logging
        4. 20.3.1.4 Documentation
      2. 20.3.2 Sensor Controller Engine (SCE)
        1. 20.3.2.1  Registers
          1.        Pipeline Hazards
        2. 20.3.2.2  Memory Architecture
          1.        Memory Access to Instructions and Data
          2.        I/O Access to Module Registers
        3. 20.3.2.3  Program Flow
          1.        Zero-Overhead Loop
        4. 20.3.2.4  Instruction Set
          1. 20.3.2.4.1 Instruction Timing
          2. 20.3.2.4.2 Instruction Prefix
          3. 20.3.2.4.3 Instructions
        5. 20.3.2.5  SCE Event Interface
        6. 20.3.2.6  Math Accelerator (MAC)
        7. 20.3.2.7  Programmable Microsecond Delay
        8. 20.3.2.8  Wake-Up Event Handling
        9. 20.3.2.9  Access to AON Domain Registers
        10. 20.3.2.10 VDDR Recharge
    4. 20.4 Digital Peripheral Modules
      1. 20.4.1 Overview
        1. 20.4.1.1 DDI Control-Configuration
      2. 20.4.2 Analog I/O Digital I/O (AIODIO)
        1. 20.4.2.1 Introduction
        2. 20.4.2.2 Functional Description
          1. 20.4.2.2.1 Mapping to DIO Pins
          2. 20.4.2.2.2 Configuration
          3. 20.4.2.2.3 GPIO Mode
          4. 20.4.2.2.4 Input Buffer
          5. 20.4.2.2.5 Data Output Source
      3. 20.4.3 Semaphore (SMPH)
        1. 20.4.3.1 Introduction
        2. 20.4.3.2 Functional Description
        3. 20.4.3.3 Semaphore Allocation in TI Software
      4. 20.4.4 SPI Master (SPIM)
        1. 20.4.4.1 Introduction
        2. 20.4.4.2 Functional Description
          1. 20.4.4.2.1 TX and RX Operations
          2. 20.4.4.2.2 Configuration
          3. 20.4.4.2.3 Timing Diagrams
      5. 20.4.5 Time-to-Digital Converter (TDC)
        1. 20.4.5.1 Introduction
        2. 20.4.5.2 Functional Description
          1. 20.4.5.2.1 Command
          2. 20.4.5.2.2 Conversion Time Configuration
          3. 20.4.5.2.3 Status and Result
          4. 20.4.5.2.4 Clock Source Selection
            1. 20.4.5.2.4.1 Counter Clock
            2. 20.4.5.2.4.2 Reference Clock
          5. 20.4.5.2.5 Start and Stop Events
          6. 20.4.5.2.6 Prescaler
        3. 20.4.5.3 Supported Measurement Types
          1. 20.4.5.3.1 Measure Pulse Width
          2. 20.4.5.3.2 Measure Frequency
          3. 20.4.5.3.3 Measure Time Between Edges of Different Events Sources
            1. 20.4.5.3.3.1 Asynchronous Counter Start – Ignore 0 Stop Events
            2. 20.4.5.3.3.2 Synchronous Counter Start – Ignore 0 Stop Events
            3. 20.4.5.3.3.3 Asynchronous Counter Start – Ignore Stop Events
            4. 20.4.5.3.3.4 Synchronous Counter Start – Ignore Stop Events
          4. 20.4.5.3.4 Pulse Counting
      6. 20.4.6 Timer01
        1. 20.4.6.1 Introduction
        2. 20.4.6.2 Functional Description
      7. 20.4.7 Timer2
        1. 20.4.7.1 Introduction
        2. 20.4.7.2 Functional Description
          1. 20.4.7.2.1 Clock Source
          2. 20.4.7.2.2 Clock Prescaler
          3. 20.4.7.2.3 Counter
          4. 20.4.7.2.4 Event Outputs
          5. 20.4.7.2.5 Channel Actions
            1. 20.4.7.2.5.1 Period and Pulse Width Measurement
            2. 20.4.7.2.5.2 Clear on Zero, Toggle on Compare Repeatedly
            3. 20.4.7.2.5.3 Set on Zero, Toggle on Compare Repeatedly
          6. 20.4.7.2.6 Asynchronous Bus Bridge
    5. 20.5 Analog Peripheral Modules
      1. 20.5.1 Overview
        1. 20.5.1.1 ADI Control-Configuration
        2. 20.5.1.2 Block Diagram
      2. 20.5.2 Analog-to-Digital Converter (ADC)
        1. 20.5.2.1 Introduction
        2. 20.5.2.2 Functional Description
          1. 20.5.2.2.1 Input Selection and Scaling
          2. 20.5.2.2.2 Reference Selection
          3. 20.5.2.2.3 ADC Sample Mode
          4. 20.5.2.2.4 ADC Clock Source
          5. 20.5.2.2.5 ADC Trigger
          6. 20.5.2.2.6 Sample FIFO
          7. 20.5.2.2.7 µDMA Interface
          8. 20.5.2.2.8 Resource Ownership and Usage
      3. 20.5.3 Comparator A (COMPA)
        1. 20.5.3.1 Introduction
        2. 20.5.3.2 Functional Description
          1. 20.5.3.2.1 Input Selection
          2. 20.5.3.2.2 Reference Selection
          3. 20.5.3.2.3 LPM Bias and COMPA Enable
          4. 20.5.3.2.4 Resource Ownership and Usage
      4. 20.5.4 Comparator B (COMPB)
        1. 20.5.4.1 Introduction
        2. 20.5.4.2 Functional Description
          1. 20.5.4.2.1 Input Selection
          2. 20.5.4.2.2 Reference Selection
          3. 20.5.4.2.3 Resource Ownership and Usage
            1. 20.5.4.2.3.1 Sensor Controller Wakeup
            2. 20.5.4.2.3.2 System CPU Wakeup
      5. 20.5.5 Reference Digital-to-Analog Converter (DAC)
        1. 20.5.5.1 Introduction
        2. 20.5.5.2 Functional Description
          1. 20.5.5.2.1 Reference Selection
          2. 20.5.5.2.2 Output Voltage Control and Range
          3. 20.5.5.2.3 Sample Clock
            1. 20.5.5.2.3.1 Automatic Phase Control
            2. 20.5.5.2.3.2 Manual Phase Control
            3. 20.5.5.2.3.3 Operational Mode Dependency
          4. 20.5.5.2.4 Output Selection
            1. 20.5.5.2.4.1 Buffer
            2. 20.5.5.2.4.2 External Load
            3. 20.5.5.2.4.3 COMPA_REF
            4. 20.5.5.2.4.4 COMPB_REF
          5. 20.5.5.2.5 LPM Bias
          6. 20.5.5.2.6 Resource Ownership and Usage
      6. 20.5.6 Current Source (ISRC)
        1. 20.5.6.1 Introduction
        2. 20.5.6.2 Functional Description
          1. 20.5.6.2.1 Programmable Current
          2. 20.5.6.2.2 Voltage Reference
          3. 20.5.6.2.3 ISRC Enable
          4. 20.5.6.2.4 Temperature Dependency
          5. 20.5.6.2.5 Resource Ownership and Usage
    6. 20.6 Event Routing and Usage
      1. 20.6.1 AUX Event Bus
        1. 20.6.1.1 Event Signals
        2. 20.6.1.2 Event Subscribers
          1. 20.6.1.2.1 Event Detection
            1. 20.6.1.2.1.1 Detection of Asynchronous Events
            2. 20.6.1.2.1.2 Detection of Synchronous Events
      2. 20.6.2 Event Observation on External Pin
      3. 20.6.3 Events From MCU Domain
      4. 20.6.4 Events to MCU Domain
      5. 20.6.5 Events From AON Domain
      6. 20.6.6 Events to AON Domain
      7. 20.6.7 µDMA Interface
    7. 20.7 Sensor Controller Alias Register Space
    8. 20.8 AUX Domain Sensor Controller and Peripherals Registers
      1. 20.8.1  ADI_4_AUX Registers
      2. 20.8.2  AUX_AIODIO Registers
      3. 20.8.3  AUX_EVCTL Registers
      4. 20.8.4  AUX_SMPH Registers
      5. 20.8.5  AUX_TDC Registers
      6. 20.8.6  AUX_TIMER01 Registers
      7. 20.8.7  AUX_TIMER2 Registers
      8. 20.8.8  AUX_ANAIF Registers
      9. 20.8.9  AUX_SYSIF Registers
      10. 20.8.10 AUX_SPIM Registers
      11. 20.8.11 AUX_MAC Registers
      12. 20.8.12 AUX_SCE Registers
  22. 21Battery Monitor and Temperature Sensor (BATMON)
    1. 21.1 Introduction
    2. 21.2 Functional Description
    3. 21.3 AON_BATMON Registers
  23. 22Universal Asynchronous Receiver/Transmitter (UART)
    1. 22.1 Introduction
    2. 22.2 Block Diagram
    3. 22.3 Signal Description
    4. 22.4 Functional Description
      1. 22.4.1 Transmit and Receive Logic
      2. 22.4.2 Baud Rate Generation
      3. 22.4.3 Data Transmission
      4. 22.4.4 Modem Handshake Support
        1. 22.4.4.1 Signaling
        2. 22.4.4.2 Flow Control
          1. 22.4.4.2.1 Hardware Flow Control (RTS and CTS)
          2. 22.4.4.2.2 Software Flow Control (Modem Status Interrupts)
      5. 22.4.5 FIFO Operation
      6. 22.4.6 Interrupts
      7. 22.4.7 Loopback Operation
    5. 22.5 Interface to µDMA
    6. 22.6 Initialization and Configuration
    7. 22.7 UART Registers
  24. 23Serial Peripheral Interface (SPI)
    1. 23.1 Introduction
    2. 23.2 Block Diagram
    3. 23.3 Signal Description
    4. 23.4 Functional Description
      1. 23.4.1 Bit Rate Generation
      2. 23.4.2 FIFO Operation
        1. 23.4.2.1 Transmit FIFO
          1. 23.4.2.1.1 Repeated Transmit Operation
        2. 23.4.2.2 Receive FIFO
        3. 23.4.2.3 FIFO Flush
      3. 23.4.3 Interrupts
      4. 23.4.4 Data Format
      5. 23.4.5 Delayed Data Sampling
      6. 23.4.6 Frame Formats
        1. 23.4.6.1 Texas Instruments Synchronous Serial Frame Format
        2. 23.4.6.2 Motorola SPI Frame Format
          1. 23.4.6.2.1 SPO Clock Polarity Bit
          2. 23.4.6.2.2 SPH Phase Control Bit
        3. 23.4.6.3 Motorola SPI Frame Format with SPO = 0 and SPH = 0
        4. 23.4.6.4 Motorola SPI Frame Format with SPO = 0 and SPH = 1
        5. 23.4.6.5 Motorola SPI Frame Format with SPO = 1 and SPH = 0
        6. 23.4.6.6 Motorola SPI Frame Format with SPO = 1 and SPH = 1
        7. 23.4.6.7 MICROWIRE Frame Format
    5. 23.5 μDMA Operation
    6. 23.6 Initialization and Configuration
    7. 23.7 SPI Registers
  25. 24Inter-Integrated Circuit (I2C)
    1. 24.1 Introduction
    2. 24.2 Block Diagram
    3. 24.3 Functional Description
      1. 24.3.1 I2C Bus Functional Overview
        1. 24.3.1.1 Start and Stop Conditions
        2. 24.3.1.2 Data Format with 7-Bit Address
        3. 24.3.1.3 Data Validity
        4. 24.3.1.4 Acknowledge
        5. 24.3.1.5 Arbitration
      2. 24.3.2 Available Speed Modes
        1. 24.3.2.1 Standard and Fast Modes
      3. 24.3.3 Interrupts
        1. 24.3.3.1 I2C Master Interrupts
        2. 24.3.3.2 I2C Slave Interrupts
      4. 24.3.4 Loopback Operation
      5. 24.3.5 Command Sequence Flow Charts
        1. 24.3.5.1 I2C Master Command Sequences
        2. 24.3.5.2 I2C Slave Command Sequences
    4. 24.4 Initialization and Configuration
    5. 24.5 I2C Registers
  26. 25Inter-IC Sound (I2S)
    1. 25.1 Introduction
    2. 25.2 Block Diagram
    3. 25.3 Signal Description
    4. 25.4 Functional Description
      1. 25.4.1 Dependencies
        1. 25.4.1.1 System CPU Deep-Sleep Mode
      2. 25.4.2 Pin Configuration
      3. 25.4.3 Serial Format Configuration
      4. 25.4.4 I2S
        1. 25.4.4.1 Register Configuration
      5. 25.4.5 Left-Justified (LJF)
        1. 25.4.5.1 Register Configuration
      6. 25.4.6 Right-Justified (RJF)
        1. 25.4.6.1 Register Configuration
      7. 25.4.7 DSP
        1. 25.4.7.1 Register Configuration
      8. 25.4.8 Clock Configuration
        1. 25.4.8.1 Internal Audio Clock Source
        2. 25.4.8.2 External Audio Clock Source
    5. 25.5 Memory Interface
      1. 25.5.1 Sample Word Length
      2. 25.5.2 Channel Mapping
      3. 25.5.3 Sample Storage in Memory
      4. 25.5.4 DMA Operation
        1. 25.5.4.1 Start-Up
        2. 25.5.4.2 Operation
        3. 25.5.4.3 Shutdown
    6. 25.6 Samplestamp Generator
      1. 25.6.1 Samplestamp Counters
      2. 25.6.2 Start-Up Triggers
      3. 25.6.3 Samplestamp Capture
      4. 25.6.4 Achieving Constant Audio Latency
    7. 25.7 Error Detection
    8. 25.8 Usage
      1. 25.8.1 Start-Up Sequence
      2. 25.8.2 Shutdown Sequence
    9. 25.9 I2S Registers
  27. 26Radio
    1. 26.1  RF Core
      1. 26.1.1 High-Level Description and Overview
    2. 26.2  Radio Doorbell
      1. 26.2.1 Special Boot Process
      2. 26.2.2 Command and Status Register and Events
      3. 26.2.3 RF Core Interrupts
        1. 26.2.3.1 RF Command and Packet Engine Interrupts
        2. 26.2.3.2 RF Core Hardware Interrupts
        3. 26.2.3.3 RF Core Command Acknowledge Interrupt
      4. 26.2.4 Radio Timer
        1. 26.2.4.1 Compare and Capture Events
        2. 26.2.4.2 Radio Timer Outputs
        3. 26.2.4.3 Synchronization with Real-Time Clock
    3. 26.3  RF Core HAL
      1. 26.3.1 Hardware Support
      2. 26.3.2 Firmware Support
        1. 26.3.2.1 Commands
        2. 26.3.2.2 Command Status
        3. 26.3.2.3 Interrupts
        4. 26.3.2.4 Passing Data
        5. 26.3.2.5 Command Scheduling
          1. 26.3.2.5.1 Triggers
          2. 26.3.2.5.2 Conditional Execution
          3. 26.3.2.5.3 Handling Before Start of Command
        6. 26.3.2.6 Command Data Structures
          1. 26.3.2.6.1 Radio Operation Command Structure
        7. 26.3.2.7 Data Entry Structures
          1. 26.3.2.7.1 Data Entry Queue
          2. 26.3.2.7.2 Data Entry
          3. 26.3.2.7.3 Pointer Entry
          4. 26.3.2.7.4 Partial Read RX Entry
        8. 26.3.2.8 External Signaling
      3. 26.3.3 Command Definitions
        1. 26.3.3.1 Protocol-Independent Radio Operation Commands
          1. 26.3.3.1.1  CMD_NOP: No Operation Command
          2. 26.3.3.1.2  CMD_RADIO_SETUP: Set Up Radio Settings Command
          3. 26.3.3.1.3  CMD_FS_POWERUP: Power Up Frequency Synthesizer
          4. 26.3.3.1.4  CMD_FS_POWERDOWN: Power Down Frequency Synthesizer
          5. 26.3.3.1.5  CMD_FS: Frequency Synthesizer Controls Command
          6. 26.3.3.1.6  CMD_FS_OFF: Turn Off Frequency Synthesizer
          7. 26.3.3.1.7  CMD_RX_TEST: Receiver Test Command
          8. 26.3.3.1.8  CMD_TX_TEST: Transmitter Test Command
          9. 26.3.3.1.9  CMD_SYNC_STOP_RAT: Synchronize and Stop Radio Timer Command
          10. 26.3.3.1.10 CMD_SYNC_START_RAT: Synchronously Start Radio Timer Command
          11. 26.3.3.1.11 CMD_COUNT: Counter Command
          12. 26.3.3.1.12 CMD_SCH_IMM: Run Immediate Command as Radio Operation
          13. 26.3.3.1.13 CMD_COUNT_BRANCH: Counter Command with Branch of Command Chain
          14. 26.3.3.1.14 CMD_PATTERN_CHECK: Check a Value in Memory Against a Pattern
        2. 26.3.3.2 Protocol-Independent Direct and Immediate Commands
          1. 26.3.3.2.1  CMD_ABORT: ABORT Command
          2. 26.3.3.2.2  CMD_STOP: Stop Command
          3. 26.3.3.2.3  CMD_GET_RSSI: Read RSSI Command
          4. 26.3.3.2.4  CMD_UPDATE_RADIO_SETUP: Update Radio Settings Command
          5. 26.3.3.2.5  CMD_TRIGGER: Generate Command Trigger
          6. 26.3.3.2.6  CMD_GET_FW_INFO: Request Information on the Firmware Being Run
          7. 26.3.3.2.7  CMD_START_RAT: Asynchronously Start Radio Timer Command
          8. 26.3.3.2.8  CMD_PING: Respond with Interrupt
          9. 26.3.3.2.9  CMD_READ_RFREG: Read RF Core Register
          10. 26.3.3.2.10 CMD_SET_RAT_CMP: Set RAT Channel to Compare Mode
          11. 26.3.3.2.11 CMD_SET_RAT_CPT: Set RAT Channel to Capture Mode
          12. 26.3.3.2.12 CMD_DISABLE_RAT_CH: Disable RAT Channel
          13. 26.3.3.2.13 CMD_SET_RAT_OUTPUT: Set RAT Output to a Specified Mode
          14. 26.3.3.2.14 CMD_ARM_RAT_CH: Arm RAT Channel
          15. 26.3.3.2.15 CMD_DISARM_RAT_CH: Disarm RAT Channel
          16. 26.3.3.2.16 CMD_SET_TX_POWER: Set Transmit Power
          17. 26.3.3.2.17 CMD_SET_TX20_POWER: Set Transmit Power of the 20 dBm PA
          18. 26.3.3.2.18 CMD_MODIFY_FS: Set New Synthesizer Frequency Without Recalibration
          19. 26.3.3.2.19 CMD_BUS_REQUEST: Request System BUS Available for RF Core
      4. 26.3.4 Immediate Commands for Data Queue Manipulation
        1. 26.3.4.1 CMD_ADD_DATA_ENTRY: Add Data Entry to Queue
        2. 26.3.4.2 CMD_REMOVE_DATA_ENTRY: Remove First Data Entry from Queue
        3. 26.3.4.3 CMD_FLUSH_QUEUE: Flush Queue
        4. 26.3.4.4 CMD_CLEAR_RX: Clear All RX Queue Entries
        5. 26.3.4.5 CMD_REMOVE_PENDING_ENTRIES: Remove Pending Entries from Queue
    4. 26.4  Data Queue Usage
      1. 26.4.1 Operations on Data Queues Available Only for Internal Radio CPU Operations
        1. 26.4.1.1 PROC_ALLOCATE_TX: Allocate TX Entry for Reading
        2. 26.4.1.2 PROC_FREE_DATA_ENTRY: Free Allocated Data Entry
        3. 26.4.1.3 PROC_FINISH_DATA_ENTRY: Finish Use of First Data Entry From Queue
        4. 26.4.1.4 PROC_ALLOCATE_RX: Allocate RX Buffer for Storing Data
        5. 26.4.1.5 PROC_FINISH_RX: Commit Received Data to RX Data Entry
      2. 26.4.2 Radio CPU Usage Model
        1. 26.4.2.1 Receive Queues
        2. 26.4.2.2 Transmit Queues
    5. 26.5  IEEE 802.15.4
      1. 26.5.1 IEEE 802.15.4 Commands
        1. 26.5.1.1 IEEE 802.15.4 Radio Operation Command Structures
        2. 26.5.1.2 IEEE 802.15.4 Immediate Command Structures
        3. 26.5.1.3 Output Structures
        4. 26.5.1.4 Other Structures and Bit Fields
      2. 26.5.2 Interrupts
      3. 26.5.3 Data Handling
        1. 26.5.3.1 Receive Buffers
        2. 26.5.3.2 Transmit Buffers
      4. 26.5.4 Radio Operation Commands
        1. 26.5.4.1 RX Operation
          1. 26.5.4.1.1 Frame Filtering and Source Matching
            1. 26.5.4.1.1.1 Frame Filtering
            2. 26.5.4.1.1.2 Source Matching
          2. 26.5.4.1.2 Frame Reception
          3. 26.5.4.1.3 ACK Transmission
          4. 26.5.4.1.4 End of Receive Operation
          5. 26.5.4.1.5 CCA Monitoring
        2. 26.5.4.2 Energy Detect Scan Operation
        3. 26.5.4.3 CSMA-CA Operation
        4. 26.5.4.4 Transmit Operation
        5. 26.5.4.5 Receive Acknowledgment Operation
        6. 26.5.4.6 Abort Background-Level Operation Command
      5. 26.5.5 Immediate Commands
        1. 26.5.5.1 Modify CCA Parameter Command
        2. 26.5.5.2 Modify Frame-Filtering Parameter Command
        3. 26.5.5.3 Enable or Disable Source Matching Entry Command
        4. 26.5.5.4 Abort Foreground-Level Operation Command
        5. 26.5.5.5 Stop Foreground-Level Operation Command
        6. 26.5.5.6 Request CCA and RSSI Information Command
    6. 26.6  Bluetooth® Low Energy
      1. 26.6.1 Bluetooth® Low Energy Commands
        1. 26.6.1.1 Command Data Definitions
          1. 26.6.1.1.1 Bluetooth® Low Energy Command Structures
        2. 26.6.1.2 Parameter Structures
        3. 26.6.1.3 Output Structures
        4. 26.6.1.4 Other Structures and Bit Fields
      2. 26.6.2 Interrupts
    7. 26.7  Data Handling
      1. 26.7.1 Receive Buffers
      2. 26.7.2 Transmit Buffers
    8. 26.8  Radio Operation Command Descriptions
      1. 26.8.1  Bluetooth® 5 Radio Setup Command
      2. 26.8.2  Radio Operation Commands for Bluetooth® Low Energy Packet Transfer
      3. 26.8.3  Coding Selection for Coded PHY
      4. 26.8.4  Parameter Override
      5. 26.8.5  Link Layer Connection
      6. 26.8.6  Slave Command
      7. 26.8.7  Master Command
      8. 26.8.8  Legacy Advertiser
        1. 26.8.8.1 Connectable Undirected Advertiser Command
        2. 26.8.8.2 Connectable Directed Advertiser Command
        3. 26.8.8.3 Non-connectable Advertiser Command
        4. 26.8.8.4 Scannable Undirected Advertiser Command
      9. 26.8.9  Bluetooth® 5 Advertiser Commands
        1. 26.8.9.1 Common Extended Advertising Packets
        2. 26.8.9.2 Extended Advertiser Command
        3. 26.8.9.3 Secondary Channel Advertiser Command
      10. 26.8.10 Scanner Commands
        1. 26.8.10.1 Scanner Receiving Legacy Advertising Packets on Primary Channel
        2. 26.8.10.2 Scanner Receiving Extended Advertising Packets on Primary Channel
        3. 26.8.10.3 Scanner Receiving Extended Advertising Packets on Secondary Channel
        4. 26.8.10.4 ADI Filtering
        5. 26.8.10.5 End of Scanner Commands
      11. 26.8.11 Initiator Command
        1. 26.8.11.1 Initiator Receiving Legacy Advertising Packets on Primary Channel
        2. 26.8.11.2 Initiator Receiving Extended Advertising Packets on Primary Channel
        3. 26.8.11.3 Initiator Receiving Extended Advertising Packets on Secondary Channel
        4. 26.8.11.4 Automatic Window Offset Insertion
        5. 26.8.11.5 End of Initiator Commands
      12. 26.8.12 Generic Receiver Command
      13. 26.8.13 PHY Test Transmit Command
      14. 26.8.14 Whitelist Processing
      15. 26.8.15 Backoff Procedure
      16. 26.8.16 AUX Pointer Processing
      17. 26.8.17 Dynamic Change of Device Address
    9. 26.9  Immediate Commands
      1. 26.9.1 Update Advertising Payload Command
    10. 26.10 Proprietary Radio
      1. 26.10.1 Packet Formats
      2. 26.10.2 Commands
        1. 26.10.2.1 Command Data Definitions
          1. 26.10.2.1.1 Command Structures
        2. 26.10.2.2 Output Structures
        3. 26.10.2.3 Other Structures and Bit Fields
      3. 26.10.3 Interrupts
      4. 26.10.4 Data Handling
        1. 26.10.4.1 Receive Buffers
        2. 26.10.4.2 Transmit Buffers
      5. 26.10.5 Radio Operation Command Descriptions
        1. 26.10.5.1 End of Operation
        2. 26.10.5.2 Proprietary Mode Setup Command
          1. 26.10.5.2.1 IEEE 802.15.4g Packet Format
        3. 26.10.5.3 Transmitter Commands
          1. 26.10.5.3.1 Standard Transmit Command, CMD_PROP_TX
          2. 26.10.5.3.2 Advanced Transmit Command, CMD_PROP_TX_ADV
        4. 26.10.5.4 Receiver Commands
          1. 26.10.5.4.1 Standard Receive Command, CMD_PROP_RX
          2. 26.10.5.4.2 Advanced Receive Command, CMD_PROP_RX_ADV
        5. 26.10.5.5 Carrier-Sense Operation
          1. 26.10.5.5.1 Common Carrier-Sense Description
          2. 26.10.5.5.2 Carrier-Sense Command, CMD_PROP_CS
          3. 26.10.5.5.3 Sniff Mode Receiver Commands, CMD_PROP_RX_SNIFF and CMD_PROP_RX_ADV_SNIFF
      6. 26.10.6 Immediate Commands
        1. 26.10.6.1 Set Packet Length Command, CMD_PROP_SET_LEN
        2. 26.10.6.2 Restart Packet RX Command, CMD_PROP_RESTART_RX
    11. 26.11 Radio Registers
      1. 26.11.1 RFC_RAT Registers
      2. 26.11.2 RFC_DBELL Registers
      3. 26.11.3 RFC_PWR Registers
  28. 27Revision History

23.7 SPI Registers

Table 23-2 lists the memory-mapped registers for the SPI registers. All register offset addresses not listed in Table 23-2 should be considered as reserved locations and the register contents should not be modified.

Table 23-2 SPI Registers
OffsetAcronymRegister NameSection
20hIIDXThis register provides the highest priority enabled interrupt index. Value 0x00 means no event pending. Interrupt 1 is the highest priority, and 31 is the least priority. That is, the least bit position that is set to 1 denotes the highest priority pending interrupt. The priority order is fixed. However, users can implement their own prioritization schemes using other registers that expose the full set of interrupts that have occurred.Section 23.7.1
28hIMASKInterrupt Mask. If a bit is set, then corresponding interrupt is un-masked. Un-masking the interrupt causes the raw interrupt to be visible in IIDX, as well as MIS.Section 23.7.2
30hRISRaw interrupt status. Reflects all pending interrupts, regardless of masking. The RIS register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the ICLR register bit even if the corresponding IMASK bit is not enabled.Section 23.7.3
38hMISMasked interrupt status. This is an AND of the IMASK and RIS registers.Section 23.7.4
40hISETInterrupt set. Allows interrupts to be set by software (useful in diagnostics and safety checks). Writing a 1 to a bit in ISET will set the event and therefore the related RIS bit also gets set. If the interrupt is enabled through the mask, then the corresponding MIS bit is also set.Section 23.7.5
48hICLRInterrupt clear. Write a 1 to clear the corresponding Interrupt.Section 23.7.6
E0hEVT_MODEEvent mode register. It is used to select whether each line is disabled, in software mode (software clears the RIS) or in hardware mode (hardware clears the RIS)Section 23.7.7
FChDESCThis register identifies the peripheral and its exact version.Section 23.7.8
100hCTL0SPI Control Register 0Section 23.7.9
104hCTL1SPI Control Register 1Section 23.7.10
108hCLKCTLClock prescaler and divider register. This register contains the settings for the Clock prescaler and divider settings.Section 23.7.11
10ChIFLSThe IFLS register is the interrupt FIFO level select register. This register can be used to define the levels at which the TX, RX FIFO interrupt flags are triggered. Out of reset, the TXIFLSEL and RXIFLSEL bits are configured so that the FIFOs trigger an interrupt at the half-way mark.Section 23.7.12
110hSTATStatus RegisterSection 23.7.13
114hCLKDIV2This register is used to specify a divide ratio of the SPI functional clock.Section 23.7.14
118hDMACRDMA Control RegisterSection 23.7.15
130hRXDATARXDATA Register. Reading this register returns value in the RX FIFO pointed by the current FIFO read pointer. If the RX FIFO is empty, the last read value is returned. Writing has not effect and is ignored.Section 23.7.16
140hTXDATATXDATA Register. Writing into this register puts the data into the TX FIFO. Reading this register returns the last written value, pointed by the current FIFO write pointer.Section 23.7.17

Complex bit access types are encoded to fit into small table cells. Table 23-3 shows the codes that are used for access types in this section.

Table 23-3 SPI Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value

23.7.1 IIDX Register (Offset = 20h) [Reset = 00000000h]

IIDX is shown in Table 23-4.

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This register provides the highest priority enabled interrupt index. Value 0x00 means no event pending. Interrupt 1 is the highest priority, and 31 is the least priority. That is, the least bit position that is set to 1 denotes the highest priority pending interrupt. The priority order is fixed. However, users can implement their own prioritization schemes using other registers that expose the full set of interrupts that have occurred.
On each read, only one interrupt is indicated. On a read, the current interrupt (highest priority) is automatically cleared by the hardware and the corresponding interrupt flag in RIS and MIS are cleared as well. After a read from the CPU (not from the debug interface), the register is updated with the next highest priority interrupt, if none are pending, then it would display 0x0.

Table 23-4 IIDX Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
7-0STATR0hInterrupt index status
0h = No interrupt pending
1h = RX FIFO Overflow Event/interrupt pending
2h = Transmit Parity Event/interrupt pending
3h = SPI Receive Time-Out Event/interrupt pending
4h = Receive Event/interrupt pending
5h = Transmit Event/interrupt pending
6h = Transmit Buffer Empty Event/interrupt pending
7h = End of Transmit Event/interrupt pending
8h = DMA Done for Receive Event/interrupt pending
9h = DMA Done for Transmit Event/interrupt pending

23.7.2 IMASK Register (Offset = 28h) [Reset = 00000000h]

IMASK is shown in Table 23-5.

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Interrupt Mask. If a bit is set, then corresponding interrupt is un-masked. Un-masking the interrupt causes the raw interrupt to be visible in IIDX, as well as MIS.

Table 23-5 IMASK Register Field Descriptions
BitFieldTypeResetDescription
31-9RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
8DMA_DONE_TXR/W0hDMA Done event for TX event mask.
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
7DMA_DONE_RXR/W0hDMA Done event for RX event mask.
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
6IDLER/W0hSPI Idle event mask.
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
5TXEMPTYR/W0hTransmit FIFO Empty event mask.
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
4TXR/W0hTransmit FIFO event mask.
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
3RXR/W0hReceive FIFO event. This interrupt is set if the selected Receive FIFO level has been reached
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
2RTOUTR/W0hSPI Receive Time-Out event mask.
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
1PERR/W0hParity error event mask.
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
0RXFIFO_OVFR/W0hRXFIFO overflow event mask.
0h = Clear Interrupt Mask
1h = Set Interrupt Mask

23.7.3 RIS Register (Offset = 30h) [Reset = 00000000h]

RIS is shown in Table 23-6.

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Raw interrupt status. Reflects all pending interrupts, regardless of masking. The RIS register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the ICLR register bit even if the corresponding IMASK bit is not enabled.

Table 23-6 RIS Register Field Descriptions
BitFieldTypeResetDescription
31-9RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
8DMA_DONE_TXR0hDMA Done event for TX. This interrupt is set if the TX DMA channel sends the DONE signal. This allows the handling of the DMA event inside the mapped peripheral.
0h = Interrupt did not occur
1h = Interrupt occurred
7DMA_DONE_RXR0hDMA Done event for RX. This interrupt is set if the RX DMA channel sends the DONE signal. This allows the handling of the DMA event inside the mapped peripheral.
0h = Interrupt did not occur
1h = Interrupt occurred
6IDLER0hSPI has completed transfers and changed into IDLE mode. This bit is set when STAT.BUSY goes low.
0h = Interrupt did not occur
1h = Interrupt occurred
5TXEMPTYR0hTransmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been move to the shift register.
0h = Interrupt did not occur
1h = Interrupt occurred
4TXR0hTransmit FIFO event. This interrupt is set if the selected Transmit FIFO level has been reached.
0h = Interrupt did not occur
1h = Interrupt occurred
3RXR0hReceive FIFO event. This interrupt is set if the selected Receive FIFO level has been reached
0h = Interrupt did not occur
1h = Interrupt occurred
2RTOUTR0hSPI Receive Time-Out event.
0h = Interrupt did not occur
1h = Interrupt occurred
1PERR0hParity error event: this bit is set if a parity error has been detected
0h = Interrupt did not occur
1h = Interrupt occurred
0RXFIFO_OVFR0hRXFIFO overflow event. This interrupt is set if an RX FIFO overflow has been detected.
0h = Interrupt did not occur
1h = Interrupt occurred

23.7.4 MIS Register (Offset = 38h) [Reset = 00000000h]

MIS is shown in Table 23-7.

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Masked interrupt status. This is an AND of the IMASK and RIS registers.

Table 23-7 MIS Register Field Descriptions
BitFieldTypeResetDescription
31-9RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
8DMA_DONE_TXR0hMasked DMA Done event for TX.
0h = Interrupt did not occur
1h = Interrupt occurred
7DMA_DONE_RXR0hMasked DMA Done event for RX.
0h = Interrupt did not occur
1h = Interrupt occurred
6IDLER0hMasked SPI IDLE mode event.
0h = Interrupt did not occur
1h = Interrupt occurred
5TXEMPTYR0hMasked Transmit FIFO Empty event.
0h = Interrupt did not occur
1h = Interrupt occurred
4TXR0hMasked Transmit FIFO event. This interrupt is set if the selected Transmit FIFO level has been reached.
0h = Interrupt did not occur
1h = Interrupt occurred
3RXR0hMasked receive FIFO event. This interrupt is set if the selected Receive FIFO level has been reached
0h = Interrupt did not occur
1h = Interrupt occurred
2RTOUTR0hMasked SPI Receive Time-Out Interrupt.
0h = Interrupt did not occur
1h = Interrupt occurred
1PERR0hMasked Parity error event: this bit if a parity error has been detected
0h = Interrupt did not occur
1h = Interrupt occurred
0RXFIFO_OVFR0hMasked RXFIFO overflow event. This interrupt is set if an RX FIFO overflow has been detected.
0h = Interrupt did not occur
1h = Interrupt occurred

23.7.5 ISET Register (Offset = 40h) [Reset = 00000000h]

ISET is shown in Table 23-8.

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Interrupt set. Allows interrupts to be set by software (useful in diagnostics and safety checks). Writing a 1 to a bit in ISET will set the event and therefore the related RIS bit also gets set. If the interrupt is enabled through the mask, then the corresponding MIS bit is also set.

Table 23-8 ISET Register Field Descriptions
BitFieldTypeResetDescription
31-9RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
8DMA_DONE_TXW0hSet DMA Done event for TX.
0h = Writing 0 has no effect
1h = Set Interrupt
7DMA_DONE_RXW0hSet DMA Done event for RX.
0h = Writing 0 has no effect
1h = Set Interrupt
6IDLEW0hSet SPI IDLE mode event.
0h = Writing 0 has no effect
1h = Set Interrupt
5TXEMPTYW0hSet Transmit FIFO Empty event.
0h = Writing 0 has no effect
1h = Set Interrupt
4TXW0hSet Transmit FIFO event.
0h = Writing 0 has no effect
1h = Set Interrupt
3RXW0hSet Receive FIFO event.
0h = Writing 0 has no effect
1h = Set Interrupt
2RTOUTW0hSet SPI Receive Time-Out event.
0h = Writing 0 has no effect
1h = Set Interrupt
1PERW0hSet Parity error event.
0h = Writing 0 has no effect
1h = Set Interrupt
0RXFIFO_OVFW0hSet RXFIFO overflow event.
0h = Writing 0 has no effect
1h = Set Interrupt

23.7.6 ICLR Register (Offset = 48h) [Reset = 00000000h]

ICLR is shown in Table 23-9.

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Interrupt clear. Write a 1 to clear the corresponding Interrupt.

Table 23-9 ICLR Register Field Descriptions
BitFieldTypeResetDescription
31-9RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
8DMA_DONE_TXW0hClear DMA Done event for TX.
0h = Writing 0 has no effect
1h = Clear Interrupt
7DMA_DONE_RXW0hClear DMA Done event for RX.
0h = Writing 0 has no effect
1h = Clear Interrupt
6IDLEW0hClear SPI IDLE mode event.
0h = Writing 0 has no effect
1h = Clear Interrupt
5TXEMPTYW0hClear Transmit FIFO Empty event.
0h = Writing 0 has no effect
1h = Clear Interrupt
4TXW0hClear Transmit FIFO event.
0h = Writing 0 has no effect
1h = Clear Interrupt
3RXW0hClear Receive FIFO event.
0h = Writing 0 has no effect
1h = Clear Interrupt
2RTOUTW0hClear SPI Receive Time-Out event.
0h = Writing 0 has no effect
1h = Clear Interrupt
1PERW0hClear Parity error event.
0h = Writing 0 has no effect
1h = Clear Interrupt
0RXFIFO_OVFW0hClear RXFIFO overflow event.
0h = Writing 0 has no effect
1h = Clear Interrupt

23.7.7 EVT_MODE Register (Offset = E0h) [Reset = 00000001h]

EVT_MODE is shown in Table 23-10.

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Event mode register. It is used to select whether each line is disabled, in software mode (software clears the RIS) or in hardware mode (hardware clears the RIS)
Note: The recommendation is to use SPI in the software mode

Table 23-10 EVT_MODE Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
1-0INT0_CFGR/W1hEvent line mode select for event corresponding to IPSTANDARD.INT_EVENT0
0h = The interrupt or event line is disabled.
1h = The interrupt or event line is in software mode. Software must clear the RIS.
2h = The interrupt or event line is in hardware mode. The hardware automatically clears the RIS flag.

23.7.8 DESC Register (Offset = FCh) [Reset = 14110010h]

DESC is shown in Table 23-11.

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This register identifies the peripheral and its exact version.

Table 23-11 DESC Register Field Descriptions
BitFieldTypeResetDescription
31-16MODULEIDR1411hModule identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness.
15-12FEATUREVERR0hFeature set version for this module instance.
11-8RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
7-4MAJREVR1hMajor revision of the IP
3-0MINREVR0hMinor revision of the IP

23.7.9 CTL0 Register (Offset = 100h) [Reset = 00000000h]

CTL0 is shown in Table 23-12.

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SPI Control Register 0

Table 23-12 CTL0 Register Field Descriptions
BitFieldTypeResetDescription
31-15RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
14CSCLRR/W0hClear shift register counter when CS gets inactive. This bit is relevant only in the slave mode, CTL1.MS = 0.
0h = Disable automatic clear of shift register when CS gets inactive.
1h = Enable automatic clear of shift register when CS gets inactive.
13-12RESERVEDR0hReserved
11-10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
9SPHR/W0hCLKOUT phase (Motorola SPI frame format only)
This bit selects the clock edge that captures data and enables it to change state. It has the most impact on the first bit transmitted by either permitting or not permitting a clock transition before the first data capture edge.
0h = Data is captured on the first clock edge transition.
1h = Data is captured on the second clock edge transition.
8SPOR/W0hCLKOUT polarity (Motorola SPI frame format only)
0h = SPI produces a steady state LOW value on the CLKOUT when data is not being transferred.
1h = SPI produces a steady state HIGH value on the CLKOUT when data is not being transferred.
7RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
6-5FRFR/W0hFrame format Select
0h = Motorola SPI frame format (3 wire mode)
1h = Motorola SPI frame format (4 wire mode)
2h = TI synchronous serial frame format
3h = National MICROWIRE frame format
4-0DSSR/W0hData Size Select.
Note:
Master mode: Values 0 - 2 are reserved and shall not be used. This will map to 4 bit mode. A value of 3h corresponds to 4-bit data (and so on).
Slave mode: DSS should be no less than 6 which means the minimum frame length is 7 bits.
3h = Data Size Select bits: 4
4h = Data Size Select bits: 5
5h = Data Size Select bits: 6
6h = Data Size Select bits: 7
7h = Data Size Select bits: 8
8h = Data Size Select bits: 9
9h = Data Size Select bits: 10
Ah = Data Size Select bits: 11
Bh = Data Size Select bits: 12
Ch = Data Size Select bits: 13
Dh = Data Size Select bits: 14
Eh = Data Size Select bits: 15
Fh = Data Size Select bits: 16
10h = Data Size Select bits: 17
11h = Data Size Select bits: 18
12h = Data Size Select bits: 19
13h = Data Size Select bits: 20
14h = Data Size Select bits: 21
15h = Data Size Select bits: 22
16h = Data Size Select bits: 23
17h = Data Size Select bits: 24
18h = Data Size Select bits: 25
19h = Data Size Select bits: 26
1Ah = Data Size Select bits: 27
1Bh = Data Size Select bits: 28
1Ch = Data Size Select bits: 29
1Dh = Data Size Select bits: 30
1Eh = Data Size Select bits: 31
1Fh = Data Size Select bits: 32

23.7.10 CTL1 Register (Offset = 104h) [Reset = 00000004h]

CTL1 is shown in Table 23-13.

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SPI Control Register 1

Table 23-13 CTL1 Register Field Descriptions
BitFieldTypeResetDescription
31-30RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
29-24RXTIMEOUTR/W0hReceive Timeout (only for Slave mode). This register defines the number of clock cycles after which the Receive Timeout interrupt is set.
A value of 0 disables this function.
0h = Smallest value
3Fh = Highest possible value
23-16REPEATTXR/W0hCounter to repeat last transfer. A value of 0 disables this feature. After a non-zero value (X) is written to this register, SPI transfer can be started with writing a data into the TX Buffer. The data will be transferred X+1 times in total. The behavior is identical as if the data were be written into the TX Buffer that many times as defined by the value here additionally.
It can be used to clean a transfer or to pull a certain amount of data by a slave. This feature can be used only in the master mode.
15-11RESERVEDR0hReserved
10FIFORSTR/W0hThis bit is used to reset transmit and receive FIFO pointers. The pointers are held at a reset value until this bit is cleared to zero.
0h = Clear FIFO pointers reset trigger
1h = Set FIFO pointers reset trigger
9-8RESERVEDR0hReserved
7PBSR/W0hParity Bit Select
0h = Bit 0 is used for Parity
1h = Bit 1 is used for Parity, Bit 0 is ignored
6PESR/W0hEven Parity Select
0h = Odd Parity mode
1h = Even Parity mode
5PENR/W0hParity enable
if enabled the last bit will be used as parity to evaluate the right transmission of the previous bits.
In case of a parity mismatch the parity error flag RIS.PER will be set.
0h = Disable Parity function
1h = Enable Parity function
4MSBR/W0hMSB first select. Controls the direction of the receive and transmit shift register.
0h = LSB first
1h = MSB first
3SODR/W0hSlave-mode: Data output disabled
This bit is relevant only in the slave mode, MS=0. In multiple-slave systems, it is possible for an SPI master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RX lines from multiple slaves could be tied together. To operate in such systems, this bitfield can be set if the SPI slave is not supposed to drive the TX line.
0h = SPI can drive the MISO output via TX in slave mode.
1h = SPI cannot drive the MISO output via TX in slave mode.
2MSR/W1hMaster or slave mode select. This bit can be modified only when SPI is disabled, CTL1.ENABLE = 0.
0h = Select Slave Mode
1h = Select Master Mode
1LBMR/W0hLoop back mode
0h = Disable loopback mode. Normal serial port operation enabled.
1h = Enable loopback mode.Output of transmit serial shifter is connected to input of receive serial shifter internally.
0ENABLER/W0hSPI enable
0h = Disable module function
1h = Enable module function

23.7.11 CLKCTL Register (Offset = 108h) [Reset = 00000000h]

CLKCTL is shown in Table 23-14.

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Clock prescaler and divider register. This register contains the settings for the Clock prescaler and divider settings.

Table 23-14 CLKCTL Register Field Descriptions
BitFieldTypeResetDescription
31-28DSAMPLER/W0hDelayed sampling. In master mode the data on the input pin will be sampled after the defined clock cycles. Note: As an example, if the SPI transmit frequency is set to 12 MHz in the master mode, DSAMPLE should be set to a value of 2
27-10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
9-0SCRR/W0hSerial clock divider:
This is used to generate the transmit and receive bit rate of the SPI.
The SPI bit rate is
(SPI's functional clock frequency)/((SCR+1)*2).
SCR is a value from 0-1023.
0h = Smallest value
3FFh = Highest possible value

23.7.12 IFLS Register (Offset = 10Ch) [Reset = 00000012h]

IFLS is shown in Table 23-15.

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The IFLS register is the interrupt FIFO level select register. This register can be used to define the levels at which the TX, RX FIFO interrupt flags are triggered. Out of reset, the TXIFLSEL and RXIFLSEL bits are configured so that the FIFOs trigger an interrupt at the half-way mark.

Table 23-15 IFLS Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
5-3RXIFLSELR/W2hSPI Receive Interrupt FIFO Level Select The trigger points for the receive interrupt are as follows:
0h = Reserved
1h = RX FIFO >= 1/4 full
2h = RX FIFO >= 1/2 full (default)
3h = RX FIFO >= 3/4 full
4h = Reserved
5h = RX FIFO is full
6h = Reserved
7h = Trigger when RX FIFO contains >= 1 byte
2-0TXIFLSELR/W2hSPI Transmit Interrupt FIFO Level Select The trigger points for the transmit interrupt are as follows:
0h = Reserved
1h = TX FIFO <= 3/4 empty
2h = TX FIFO <= 1/2 empty (default)
3h = TX FIFO <= 1/4 empty
4h = Reserved
5h = TX FIFO is empty
6h = Reserved
7h = Trigger when TX FIFO has >= 1 byte free

23.7.13 STAT Register (Offset = 110h) [Reset = 0000000Fh]

STAT is shown in Table 23-16.

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Status Register

Table 23-16 STAT Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
4BUSYR0hBusy
0h = SPI is in idle mode.
1h = SPI is currently transmitting and/or receiving data, or transmit FIFO is not empty.
3RNFR1hReceive FIFO not full
0h = Receive FIFO is full.
1h = Receive FIFO is not full.
2RFER1hReceive FIFO empty.
0h = Receive FIFO is not empty.
1h = Receive FIFO is empty.
1TNFR1hTransmit FIFO not full
0h = Transmit FIFO is full.
1h = Transmit FIFO is not full.
0TFER1hTransmit FIFO empty.
0h = Transmit FIFO is not empty.
1h = Transmit FIFO is empty.

23.7.14 CLKDIV2 Register (Offset = 114h) [Reset = 00000000h]

CLKDIV2 is shown in Table 23-17.

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This register is used to specify a divide ratio of the SPI functional clock.

Table 23-17 CLKDIV2 Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
2-0RATIOR/W0hSelects divide ratio of module clock
0h = Do not divide clock source
1h = Divide clock source by 2
2h = Divide clock source by 3
3h = Divide clock source by 4
4h = Divide clock source by 5
5h = Divide clock source by 6
6h = Divide clock source by 7
7h = Divide clock source by 8

23.7.15 DMACR Register (Offset = 118h) [Reset = 00000000h]

DMACR is shown in Table 23-18.

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DMA Control Register

Table 23-18 DMACR Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
1TXDMAER/W0hTransmit FIFO DMA enable when set.
0RXDMAER/W0hReceive FIFO DMA enable when set.

23.7.16 RXDATA Register (Offset = 130h) [Reset = 00000000h]

RXDATA is shown in Table 23-19.

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RXDATA Register. Reading this register returns value in the RX FIFO pointed by the current FIFO read pointer. If the RX FIFO is empty, the last read value is returned. Writing has not effect and is ignored.

Table 23-19 RXDATA Register Field Descriptions
BitFieldTypeResetDescription
31-0DATAR0hReceived Data

23.7.17 TXDATA Register (Offset = 140h) [Reset = 00000000h]

TXDATA is shown in Table 23-20.

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TXDATA Register. Writing into this register puts the data into the TX FIFO. Reading this register returns the last written value, pointed by the current FIFO write pointer.

Table 23-20 TXDATA Register Field Descriptions
BitFieldTypeResetDescription
31-0DATAR/W0hTransmit Data