SWCU194 March 2023 CC1314R10 , CC1354P10 , CC1354R10 , CC2674P10 , CC2674R10
The fault status registers indicate the cause of a fault. For BusFaults, MemManage faults, and SecureFaults, the fault address register indicates the address that is accessed by the operation that caused the fault.
The processor has two physical fault address registers. One shared between the MMFAR_S (CPU_SCB:MMFAR), CPU_SAU:SFAR, and CPU_SCB:BFAR (only if AIRCR.BFHFNMINS is set to 0), and the other shared between the MMFAR_NS (CPU_SCB:MMFAR) and CPU_SCB:BFAR (only if AIRCR.BFHFNMINS is set to 1). These are targeted by Secure and Non-secure faults respectively.
For each physical fault address register, it is only possible to report the address of one fault at a time.
Each fault address register is updated when one of the *FARVALID bits is set for their respective faults in the associated *FSR register. BFARVALID is located in CPU_SCB:CFSR and SFARVALID is located in CPU_SAU:SFSR. Any fault that targets a fault address register with one of its *FARVALID bits already set does not update the fault address. The *FARVALID bits must be cleared before another fault address can be reported.