SWCU194 March 2023 CC1314R10 , CC1354P10 , CC1354R10 , CC2674P10 , CC2674R10
Three main phases can be distinguished:
Initialization of the engine and start processing the first part of the AAD data.
Prepare the engine for interruption and retrieve the intermediate processing state.
Restore the intermediate processing state and start processing the next or last AAD data blocks.
-- initialization and process until interruption --
// configure the master control module
write ALGSEL 0x00000002 // enable the DMA path to the AES engine
write IRQCLR 0x00000001 // clear any outstanding events
// configure the key store to provide a pre-loaded AES key
write KEYREADAREA 0x00000000 // load the key from ram area 0 (NOTE: The key must
// be pre-loaded to this area)
wait KEYREADAREA[31] == ’0’ // wait until the key is loaded to the AES module
check IRQSTAT[29] == ‘0’ // check that the key is loaded without errors
// write zeros to KEY3
write AESKEY3_0
...
write AESKEY3_3
// write initial IV
write AESIV_0
...
write AESIV_3
// configure the AES engine
write AESCTL = 0b0010_0000_0000_0011_0000_0000_0100_1100 // program AES-GCM-128
// encryption (autonomous)
write AESDATALEN0 // write the length of the crypto block (lo)
write AESDATALEN1 // write the length of the crypto block (hi) (may
// be non-block size aligned)
write AESAUTHLEN // write the length of the AAD data block (may be
// non-block size aligned)
// configure DMAC to fetch the first part of AAD data
write DMACH0CTRL 0x000000001 // enable DMA channel 0
write DMACH0EXTADDR <address> // base address of the AAD data in ext. memory
write DMACH0DMALENGTH <length> // AAD data length in bytes, equal to the AAD
// length len({AAD data}) (may be non-block size aligned)
// wait for completion of the AAD data transfer
wait IRQSTAT[1] == ’1’ // wait for DMA_IN_DONE
check IRQSTAT[31] == ‘0’ // check for the absence of errors
-- interrupt processing and store the engine state in the AAD phase --
// configure the AES engine with get_digest
write AESCTL = 0b0010_1000_0000_0011_0000_0000_0100_1100 // program AES-GCM-128
// encryption (autonomous)
// read intermediate tag
wait AESCTL[30] == ’1’ // wait for the SAVED_CONTEXT_RDY bit [30]
read AESTAGOUT_0
...
read AESTAGOUT_3
// read intermediate block counter
read AESBLKCNT0
read AESBLKCNT1
-- restore and continue an interrupted operation in the AAD phase --
// configure the key store to provide a pre-loaded AES key
write KEYREADAREA 0x00000000 // load the key from ram area 0 (NOTE: The key
// must be pre-loaded to this area)
wait KEYREADAREA[31] == ’0’ // wait until the key is loaded to the AES module
check IRQSTAT[29] == ‘0’ // check that the key is loaded without errors
// write intermediate tag to KEY3
write AESKEY3_0
...
write AESKEY3_3
// write initial IV
write AESIV_0
...
write AESIV_3
// configure the AES engine with gcm_ccm_continue_aad
write AESCTL = 0b0010_0100_0000_0011_0000_0000_0100_1100 // program AES-GCM-128
// encryption (autonomous)
write AESDATALEN0 // write the length of the crypto block (lo)
write AESDATALEN1 // write the length of the crypto block (hi) (may
// be non-block size aligned)
// write intermediate block counter
write AESBLKCNT0
write AESBLKCNT1
write AESAUTHLEN // write the length of the AAD data block (may be
// non-block size aligned)
// configure DMAC to fetch the second part of AAD data
write DMACH0CTRL 0x000000001 // enable DMA channel 0
write DMACH0EXTADDR <address> // base address of the AAD data in ext. memory
write DMACH0DMALENGTH <length> // AAD data length in bytes, equal to the AAD
// length len({AAD data}) (may be non-block size aligned)
// wait for completion of the AAD data transfer
wait IRQSTAT[1] == ’1’ // wait for DMA_IN_DONE
check IRQSTAT[31] == ‘0’ // check for the absence of errors
// configure DMAC to process the payload data
write DMACH0CTRL 0x000000001 // enable DMA channel 0
write DMACH0EXTADDR <address> // base address of the payload data in ext. memory
write DMACH0DMALENGTH <length> // payload data length in bytes, equal to the
// payload length len({crypto_data})
// (may be non-block size aligned)
write DMACH1CTL 0x000000001 // enable DMA channel 1
write DMACH1EXTADDR <address> // base address of the output data buffer
write DMACH1LEN <length> // output data length in bytes, equal to the
// result data length len({crypto data})
// (may be non-block size aligned)
// wait for completion
wait IRQSTAT[0] == ’1’ // wait for operation completed
check IRQSTAT[31] == ‘0’ // check for the absence of errors
write ALGSEL 0x00000000 // disable the master control/DMA clock
// read tag
wait AESCTL[30] == ’1’ // wait for the SAVED_CONTEXT_RDY bit [30]
read AESTAGOUT_0
...
read AESTAGOUT_3 // this read clears the SAVED_CONTEXT_RDY flag
// end of algorithm