SWCU194 March 2023 CC1314R10 , CC1354P10 , CC1354R10 , CC2674P10 , CC2674R10
Table 2-1 shows the processor core register set summary. Each of these registers is 32 bits wide. Some of the registers are banked. The Secure view of these registers is available when the Cortex-M33 processor is in Secure state and the Non-secure view when Cortex-M33 processor is in Non-secure state.
Name | Description |
---|---|
R0 - R12 | R0-R12 are general-purpose registers for data operations |
MSP (R13) |
The Stack Pointer (SP) is register R13. In Thread mode, the CONTROL register indicates which stack pointer to use, Main Stack Pointer (MSP) or Process Stack Pointer (PSP). There are two MSP registers in the Cortex-M33 processor:
There are two PSP registers in the Cortex-M33 processor:
|
PSP (R13) | |
MSPLIM |
The stack limit registers limit the extent to which the MSP and PSP registers can descend respectively. There are two MSPLIM registers in the Cortex-M33 processor:
There are two PSPLIM registers in the Cortex-M33 processor:
|
PSPLIM | |
LR (R14) | The Link Register (LR) is register R14 and stores the return information for subroutines, function calls, and exceptions. |
PC (R15) | The Program Counter (PC) is register R15 and contains the current program address |
PSR |
The Program Status Register (PSR) combines:
These registers provide different views of the PSR |
PRIMASK |
The PRIMASK register prevents activation of exceptions with configurable priority. There are two PRIMASK registers in the Cortex-M33 processor:
|
BASEPRI |
The BASEPRI register defines the minimum priority for exception processing. There are two BASEPRI registers in the Cortex-M33 processor:
|
FAULTMASK |
The FAULTMASK register prevents activation of all exceptions except for NON-MASKABLE INTERRUPT (NMI) and optionally Secure HardFault. There are two FAULTMASK registers in the Cortex-M33 processor:
|
CONTROL |
The CONTROL register controls the stack used, and optionally the privilege level, when the processor is in Thread mode. There are two CONTROL registers in the Cortex-M33 processor:
|