SWCU194 March 2023 CC1314R10 , CC1354P10 , CC1354R10 , CC2674P10 , CC2674R10
This channel action continuously captures period and pulse width of the signal selected by CHnCCFG.CAPT_SRC relative to the signal edge given by CHnCCFG.EDGE. The channel requests to set enabled events when CHnCC.VALUE contains signal period and CHnPCC.VALUE contains signal pulse width.
The channel function synchronizes the timer counter to the selected signal edge of the incoming signal. Hence:
For further description, see AUX_TIMER2:CHnEVCFG.CCACT in Section 20.8.7.
The timer measures signal period and pulse width of two different signals A and B. In the following example, it is assumed that both signals have periods less than the counter range. Hence, time-out detection as described in the register documentation is not required. Configure as follows:
Figure 20-25 shows how the timer counter first synchronizes to signal A. Channel 0 then captures the high phase of signal A into CH0PCC at time t0. Finally, the period of signal A is captured in CH0CC at time t1. At the same time, Channel 0 sets the event output 0 high, and the timer counter starts to synchronize to signal B. Channel 1 then captures the low phase of signal B into CH1PCC at time t2. Finally, the period of signal B is captured in CH1CC at time t3. At the same time, channel 1 sets the event output 1 high, and the timer counter starts to synchronize to signal A. The sequence then repeats itself until it is stopped by the user.