SWCU194 March 2023 CC1314R10 , CC1354P10 , CC1354R10 , CC2674P10 , CC2674R10
The FLASH memory consists of a large MAIN region and several smaller regions, including FCFG, CCFG, TRIM and ENGR. The FCFG and CCFG regions can also be referred to as NONMAIN regions.
Each region of the FLASH memory is organized as a set of 2 KB blocks that can be individually erased. Programming the FLASH by changing bits from 1 to 0 can be done in the following increments:
One 128-bit word
Two 128-bit words
Four 128-bit words
Erasing a block causes the entire contents of the block to be reset to all 1s. The 2 KB blocks are paired with sets of other 2 KB blocks that can be individually protected by being marked as read-only. Read-only blocks cannot be erased or programmed, which protects the contents of those blocks from being modified. There are separate lock bits for the MAIN, FCFG and CCFG, and these bits a located in FLASH and NVMNW.
The TRIM and ENGR regions of the flash are locked and are consequently inaccessible for program and erase.
There is a restriction on how many write operations are allowed to a FLASH row between erases. A row is comprised of 2048 bits (or 256 bytes). The FLASH memory is divided evenly into physical rows. One may perform a maximum of 83 write operations within a row between erases. If more than 83 write operations are performed before re-erasure, one may see unwritten bits in the row that are erased (in a logic 1 state) become programmed (change to a logic 0 state). User software must take care of this restriction, there is no hardware that checks and informs if this restriction is violated.
The FLASH block is mainly clocked by the 48 MHz system clock.