SWCU194 March 2023 CC1314R10 , CC1354P10 , CC1354R10 , CC2674P10 , CC2674R10
The GPTM is placed into concatenated mode by writing a 0x0 to the GPT:CFG.CFG bit field. For this configurations, certain registers are concatenated to form pseudo 32-bit registers. These registers include the following:
In the 32-bit modes, the GPTM translates a 32-bit write access to the GPT:TAILR register into a write access to both the GPT:TAILR and the GPT:TBILR registers. The resulting word ordering for such a write operation is: GPTMTBILR[15:0]:GPTMTAILR[15:0]. Likewise, a 32-bit read access to GPT:TAR register returns the value: GPTMTBR[15:0]:GPTMTAR[15:0]. A 32-bit read access to GPT:TAV returns the value: GPTMTBV[15:0]:GPTMTAV[15:0].