SWCU194 March 2023 CC1314R10 , CC1354P10 , CC1354R10 , CC2674P10 , CC2674R10
The SPI includes a programmable bit rate clock divider and prescaler to generate the serial output clock.
The serial bit rate is derived by dividing down the input clock. First, the clock is divided by a division RATIO from 1 to 8, which is programmed in SPI:CLKDIV2 (1 means that the clock is not divided). The clock is further divided by a value from 1 to 1024, which is 1 + SCR, where SCR is the value programmed in SPI:CLKCTL. See Section 23.7 for details on the SPI registers.
Equation 8 defines the frequency of the output clock SPIn_CLK.
For both master and slave modes, the core clock (PERDMACLK) must be at least two times faster than SPIn_CLK.