SPRUIX0D February   2021  – August 2021

 

  1.   Trademarks
  2. 1Introduction
    1. 1.1 EVM Revisions and Assembly Variants
  3. 2Important Usage Notes
    1. 2.1 Power-On Usage Note
  4. 3System Description
    1. 3.1 Key Features
    2. 3.2 Functional Block Diagram
    3. 3.3 Power-On/Off Procedures
      1. 3.3.1 Power-On Procedure
      2. 3.3.2 Power-Off Procedure
    4. 3.4 Peripheral and Major Component Description
      1. 3.4.1  Clocking
        1. 3.4.1.1 Ethernet PHY Clock
        2. 3.4.1.2 AM64x/AM243x Clock
        3. 3.4.1.3 PCIe Clock
      2. 3.4.2  Reset
      3. 3.4.3  Power
        1. 3.4.3.1 Power Input
        2. 3.4.3.2 Reverse Polarity Protection
        3. 3.4.3.3 Current Monitoring
        4. 3.4.3.4 Power Supply
        5. 3.4.3.5 Power Sequencing
        6. 3.4.3.6 AM64x/AM243x Power
      4. 3.4.4  Configuration
        1. 3.4.4.1 Boot Modes
      5. 3.4.5  JTAG
      6. 3.4.6  Test Automation
      7. 3.4.7  UART Interfaces
      8. 3.4.8  Memory Interfaces
        1. 3.4.8.1 DDR4 Interface
        2. 3.4.8.2 MMC Interfaces
          1. 3.4.8.2.1 Micro SD Interface
          2. 3.4.8.2.2 eMMC Interface
        3. 3.4.8.3 OSPI Interface
        4. 3.4.8.4 SPI EEPROM Interface
        5. 3.4.8.5 Board ID EEPROM Interface
      9. 3.4.9  Ethernet Interface
        1. 3.4.9.1 DP83867 PHY Default Configuration
        2. 3.4.9.2 DP83869 PHY Default Configuration
        3. 3.4.9.3 Ethernet LED
      10. 3.4.10 Display Interface
      11. 3.4.11 USB 2.0 Interface
      12. 3.4.12 PCIe Interface
      13. 3.4.13 High Speed Expansion Interface
      14. 3.4.14 CAN Interface
      15. 3.4.15 Interrupt
      16. 3.4.16 ADC Interface
      17. 3.4.17 Safety Connector
      18. 3.4.18 SPI Interfaces
      19. 3.4.19 I2C Interfaces
      20. 3.4.20 FSI Interface
  5. 4Known Issues and Modifications
    1. 4.1 Issue 1 - Embedded XDS110 Connection to AM64x Target in CCS
    2. 4.2 Issue 2 - MDIO Ethernet PHY Communications
    3. 4.3 Issue 3 - DC Barrel Jack Warning when Hot-Plugging
  6. 5References
  7. 6Revision History

3.4.6 Test Automation

A Test automation header J38 is provided to allow an external controller to control the power on/off, boot modes, reset functionality and current measurement to support automated testing. The test automation header includes four GPIOs, two I2C interfaces. The basic controls as shown in Table 3-16.

Table 3-16 List of Signals Routed to Test Automation Header
Signal Signal Type Function
POWER_DOWN GPIO Instructs the EVM to power down all circuits
POR GPIO Creates a PORz into the AM64x SoC
WARM_RESET GPIO Creates a RESETz into the AM64x SoC
GPIO1 GPIO GPIO for communication with AM64x SoC
GPIO2 GPIO Connected to I2C IO Expander
GPIO3 GPIO Used to Enable the BOOTMODE Buffer
GPIO4 GPIO Used to Reset the Boot mode IO Expander
I2C0 I2C Commnicates with Boot mode I2C buffer
I2C2 I2C Communicates with INA226 current measurement devices

One of the I2C interface from Test automation header is connected to an I2C IO expander, which can drive the Boot mode pins of the processor.

Note: The bootmode selection switches should be in the OFF condition and GPIO3 should be set to logic low to enable this mode.

The other I2C interface is connected to the current measurement and temperature sensing devices present on the I2C1 port of the SoC.

The Test Automation connector is used by Texas Instruments for control of software regression testing and comparative power measurements. The connector is provided to allow customers to develop their own testing and power measurements of customer applications.

Note: The power measurements are not a substitute for the AM64x/AM243x Power Estimation Tool and should not be used for the design of power supply solutions.

Power measurements will vary based on silicon process and environment and measurements should only be used for comparison with other measurements taken on the same EVM.

GUID-2785B313-36F5-4B83-8CB3-8DB6B2C49A24-low.png Figure 3-12 Test Automation Header
Table 3-17 Test Automation Header (J38) Pin-out
Pin No. Signal IO Direction (to CP board)
1 VCC3V3_1 Power (out)
2 VCC3V3_1 Power (out)
3 VCC3V3_1 Power (out)
4 NC NA
5 NC NA
6 NC NA
7 DGND Ground
8 NC NA
9 NC NA
10 NC NA
11 NC NA
12 NC NA
13 NC NA
14 NC NA
15 NC NA
16 DGND Ground
17 NC NA
18 NC NA
19 NC NA
20 NC NA
21 NC NA
22 NC NA
23 NC NA
24 NC NA
25 DGND Ground
26 TEST_POWERDOWN Input
27 TEST_PORz Input
28 TEST_WARMRESETn Input
29 NC NA
30 TEST_GPIO1 Bidirectional
31 TEST_GPIO2 Bidirectional
32 TEST_GPIO3 Input
33 TEST_GPIO4 Input
34 DGND Ground
35 NC NA
36 SOC_I2C1_SCL Bidirectional
37 BOOTMODE_I2C_SCL Bidirectional
38 SOC_I2C1_SDA Bidirectional
39 BOOTMODE_I2C_SDA Bidirectional
40 DGND Ground
41 DGND Ground
42 DGND Ground