SPRUIX0D February   2021  – August 2021

 

  1.   Trademarks
  2. 1Introduction
    1. 1.1 EVM Revisions and Assembly Variants
  3. 2Important Usage Notes
    1. 2.1 Power-On Usage Note
  4. 3System Description
    1. 3.1 Key Features
    2. 3.2 Functional Block Diagram
    3. 3.3 Power-On/Off Procedures
      1. 3.3.1 Power-On Procedure
      2. 3.3.2 Power-Off Procedure
    4. 3.4 Peripheral and Major Component Description
      1. 3.4.1  Clocking
        1. 3.4.1.1 Ethernet PHY Clock
        2. 3.4.1.2 AM64x/AM243x Clock
        3. 3.4.1.3 PCIe Clock
      2. 3.4.2  Reset
      3. 3.4.3  Power
        1. 3.4.3.1 Power Input
        2. 3.4.3.2 Reverse Polarity Protection
        3. 3.4.3.3 Current Monitoring
        4. 3.4.3.4 Power Supply
        5. 3.4.3.5 Power Sequencing
        6. 3.4.3.6 AM64x/AM243x Power
      4. 3.4.4  Configuration
        1. 3.4.4.1 Boot Modes
      5. 3.4.5  JTAG
      6. 3.4.6  Test Automation
      7. 3.4.7  UART Interfaces
      8. 3.4.8  Memory Interfaces
        1. 3.4.8.1 DDR4 Interface
        2. 3.4.8.2 MMC Interfaces
          1. 3.4.8.2.1 Micro SD Interface
          2. 3.4.8.2.2 eMMC Interface
        3. 3.4.8.3 OSPI Interface
        4. 3.4.8.4 SPI EEPROM Interface
        5. 3.4.8.5 Board ID EEPROM Interface
      9. 3.4.9  Ethernet Interface
        1. 3.4.9.1 DP83867 PHY Default Configuration
        2. 3.4.9.2 DP83869 PHY Default Configuration
        3. 3.4.9.3 Ethernet LED
      10. 3.4.10 Display Interface
      11. 3.4.11 USB 2.0 Interface
      12. 3.4.12 PCIe Interface
      13. 3.4.13 High Speed Expansion Interface
      14. 3.4.14 CAN Interface
      15. 3.4.15 Interrupt
      16. 3.4.16 ADC Interface
      17. 3.4.17 Safety Connector
      18. 3.4.18 SPI Interfaces
      19. 3.4.19 I2C Interfaces
      20. 3.4.20 FSI Interface
  5. 4Known Issues and Modifications
    1. 4.1 Issue 1 - Embedded XDS110 Connection to AM64x Target in CCS
    2. 4.2 Issue 2 - MDIO Ethernet PHY Communications
    3. 4.3 Issue 3 - DC Barrel Jack Warning when Hot-Plugging
  6. 5References
  7. 6Revision History

3.4.8.5 Board ID EEPROM Interface

The GP EVM includes an onboard EEPROM (U7). This EEPROM holds identifying information include the EVM version and serial number. PHY MAC ID and other static information about the EVM are also stored in this memory.

The Board ID memory shall be configured to respond to address 0x50 and 0X51 programmed with the header description and DDR information of this card. AT24CM01 from Microchip is used, this will be interfaced to I2C0 port of the SOCI2C address of the EEPROM can be modified by driving the A0, A1, A2 pins to LOW. The first 259 bytes of addressable EEPROM memory are preprogrammed with identification information for each board. The remaining 32509 bytes are available to the user for data or code storage.

Table 3-18 Board ID Memory Header Information
Header Field Name Size (bytes) Comments
EE3355AA MAGIC 4 Magic Number
TYPE 1 Fixed length and variable position board ID header
2 Size of payload
BRD_INFO TYPE 1 Payload type
Length 2 Offset to next header
Board_Name 16 Name of the board
Design_rev 2 Revision number of the design
PROC_Nbr 4 PROC number
Variant 2 Design variant number
PCB_Rev 2 Revision number of the PCB
SCHBOM_Rev 2 Revision number of the schematic
SWR_Rev 2 First software release number
VendorID 2
Build_Week 2 Week of the year of production
Build_Year 2 Year of production
BoardID 6
Serial_Nbr 4 Incrementing board number
DDR_INFO TYPE 1
Length 2 Offset to next header
DDR control 2 DDR Control Word
MAC_ADDR TYPE 1 Payload type
Length 2 Size of payload
MAC control 2 MAC header control word
MAC_adrs 192 MAC address of AM64x/AM243x PRG2
END_LIST TYPE 1 End Marker