SPRUIX0D February   2021  – August 2021

 

  1.   Trademarks
  2. 1Introduction
    1. 1.1 EVM Revisions and Assembly Variants
  3. 2Important Usage Notes
    1. 2.1 Power-On Usage Note
  4. 3System Description
    1. 3.1 Key Features
    2. 3.2 Functional Block Diagram
    3. 3.3 Power-On/Off Procedures
      1. 3.3.1 Power-On Procedure
      2. 3.3.2 Power-Off Procedure
    4. 3.4 Peripheral and Major Component Description
      1. 3.4.1  Clocking
        1. 3.4.1.1 Ethernet PHY Clock
        2. 3.4.1.2 AM64x/AM243x Clock
        3. 3.4.1.3 PCIe Clock
      2. 3.4.2  Reset
      3. 3.4.3  Power
        1. 3.4.3.1 Power Input
        2. 3.4.3.2 Reverse Polarity Protection
        3. 3.4.3.3 Current Monitoring
        4. 3.4.3.4 Power Supply
        5. 3.4.3.5 Power Sequencing
        6. 3.4.3.6 AM64x/AM243x Power
      4. 3.4.4  Configuration
        1. 3.4.4.1 Boot Modes
      5. 3.4.5  JTAG
      6. 3.4.6  Test Automation
      7. 3.4.7  UART Interfaces
      8. 3.4.8  Memory Interfaces
        1. 3.4.8.1 DDR4 Interface
        2. 3.4.8.2 MMC Interfaces
          1. 3.4.8.2.1 Micro SD Interface
          2. 3.4.8.2.2 eMMC Interface
        3. 3.4.8.3 OSPI Interface
        4. 3.4.8.4 SPI EEPROM Interface
        5. 3.4.8.5 Board ID EEPROM Interface
      9. 3.4.9  Ethernet Interface
        1. 3.4.9.1 DP83867 PHY Default Configuration
        2. 3.4.9.2 DP83869 PHY Default Configuration
        3. 3.4.9.3 Ethernet LED
      10. 3.4.10 Display Interface
      11. 3.4.11 USB 2.0 Interface
      12. 3.4.12 PCIe Interface
      13. 3.4.13 High Speed Expansion Interface
      14. 3.4.14 CAN Interface
      15. 3.4.15 Interrupt
      16. 3.4.16 ADC Interface
      17. 3.4.17 Safety Connector
      18. 3.4.18 SPI Interfaces
      19. 3.4.19 I2C Interfaces
      20. 3.4.20 FSI Interface
  5. 4Known Issues and Modifications
    1. 4.1 Issue 1 - Embedded XDS110 Connection to AM64x Target in CCS
    2. 4.2 Issue 2 - MDIO Ethernet PHY Communications
    3. 4.3 Issue 3 - DC Barrel Jack Warning when Hot-Plugging
  6. 5References
  7. 6Revision History

3.4.5 JTAG

The GP EVM includes XDS110 class embedded JTAG emulation through the micro B connector J28. It also has an optional TI20 pin (J25) connector to support external JTAG emulation. When an external emulator is connected, internal emulation circuitry will be disabled.

The design includes the footprint for a MIPI60 (J33) connector with connections for JTAG and trace capabilities. The trace pins are pinmuxed with GPMC signals which, by default, are connected to HSE connector on the processor board. Resistor networks are used to steer these signals to either the HSE connector or to the MIPI60 connector. The MIPI60 is not installed as delivered.

Resistor options are provided to connect these signals to the HSE or Trace connector as mentioned in the Table 3-13.

The pinout of TI20 pin connector and MIPI60 pin connector are given in Table 3-13 and Table 3-15, respectively.

Table 3-13 Selection of HSE Connector and JTAG TRACE Functionality
Signals Selected Mount Un Mount

HSE Connector

(default)

 RA1 RA2
RA3 RA4
RA5 RA6
R390 R391
R393 R392
JTAG Trace signals to J33 RA2 RA1
RA4 RA3
RA6 RA5
R391 R390
R392 R393
Table 3-14 TI20 Pin Connector (J25) Pin-Out
Pin No. Signal Pin No. Signal
1 JTAG_CTI_TMS 11 JTAG_CTI_TCK
2 JTAG_TRSTN 12 DGND
3 JTAG_CTI_TDI 13 JTAG_EMU0
4 JTAG_TDIS 14 JTAG_EMU1
5 VCC_3V3_SYS 15 JTAG_EMU_RSTN
6 NC 16 DGND
7 JTAG_TDO 17 NC
8 SEL_XDS110_INV 18 NC
9 JTAG_CTI_RTCK 19 NC
10 DGND 20 DGND
GUID-F28DCCC5-07EC-4E31-9332-80A941DB4787-low.png Figure 3-11 JTAG Interface
Table 3-15 TI 60-Pin Connector (J33) Pin-Out
Pin No. Signal Pin No. Signal
1 VCC3V3_R 31 MIPI_TRC_DAT06
2 MIPI_TMS_R 32 NC
3 JTAG_MIPI_TCK 33 MIPI_TRC_DAT07
4 MIPI_TDO_R 34 NC
5 MIPI_TDI_R 35 MIPI_TRC_DAT08
6 MIPI_EMU_RSTn 36 NC
7 MIPI_RTCK 37 MIPI_TRC_DAT09
8 MIPI_TRST#_R 38 JTAG_MIPI_EMU0
9 NC 39 MIPI_TRC_DAT10
10 NC 40 JTAG_MIPI_EMU1
11 NC 41 MIPI_TRC_DAT11
12 VCC_3V3_MIPI 42 NC
13 MIPI_TRC_CLK 43 MIPI_TRC_DAT12
14 NC 44 NC
15 DGND 45 MIPI_TRC_DAT13
16 DGND 46 NC
17 MIPI_TRC_CTL 47 MIPI_TRC_DAT14
18 MIPI_TRC_DAT19 48 NC
19 MIPI_TRC_DAT00 49 MIPI_TRC_DAT15
20 MIPI_TRC_DAT20 50 NC
21 MIPI_TRC_DAT01 51 MIPI_TRC_DAT16
22 MIPI_TRC_DAT21 52 NC
23 MIPI_TRC_DAT02 53 MIPI_TRC_DAT17
24 MIPI_TRC_DAT22 54 NC
25 MIPI_TRC_DAT03 55 MIPI_TRC_DAT18
26 MIPI_TRC_DAT23 56 NC
27 MIPI_TRC_DAT04 57 DGND
28 NC 58 SEL_XDS100_INV
29 MIPI_TRC_DAT05 59 NC
30 NC 60 NC