SPRUIX0D February   2021  – August 2021

 

  1.   Trademarks
  2. 1Introduction
    1. 1.1 EVM Revisions and Assembly Variants
  3. 2Important Usage Notes
    1. 2.1 Power-On Usage Note
  4. 3System Description
    1. 3.1 Key Features
    2. 3.2 Functional Block Diagram
    3. 3.3 Power-On/Off Procedures
      1. 3.3.1 Power-On Procedure
      2. 3.3.2 Power-Off Procedure
    4. 3.4 Peripheral and Major Component Description
      1. 3.4.1  Clocking
        1. 3.4.1.1 Ethernet PHY Clock
        2. 3.4.1.2 AM64x/AM243x Clock
        3. 3.4.1.3 PCIe Clock
      2. 3.4.2  Reset
      3. 3.4.3  Power
        1. 3.4.3.1 Power Input
        2. 3.4.3.2 Reverse Polarity Protection
        3. 3.4.3.3 Current Monitoring
        4. 3.4.3.4 Power Supply
        5. 3.4.3.5 Power Sequencing
        6. 3.4.3.6 AM64x/AM243x Power
      4. 3.4.4  Configuration
        1. 3.4.4.1 Boot Modes
      5. 3.4.5  JTAG
      6. 3.4.6  Test Automation
      7. 3.4.7  UART Interfaces
      8. 3.4.8  Memory Interfaces
        1. 3.4.8.1 DDR4 Interface
        2. 3.4.8.2 MMC Interfaces
          1. 3.4.8.2.1 Micro SD Interface
          2. 3.4.8.2.2 eMMC Interface
        3. 3.4.8.3 OSPI Interface
        4. 3.4.8.4 SPI EEPROM Interface
        5. 3.4.8.5 Board ID EEPROM Interface
      9. 3.4.9  Ethernet Interface
        1. 3.4.9.1 DP83867 PHY Default Configuration
        2. 3.4.9.2 DP83869 PHY Default Configuration
        3. 3.4.9.3 Ethernet LED
      10. 3.4.10 Display Interface
      11. 3.4.11 USB 2.0 Interface
      12. 3.4.12 PCIe Interface
      13. 3.4.13 High Speed Expansion Interface
      14. 3.4.14 CAN Interface
      15. 3.4.15 Interrupt
      16. 3.4.16 ADC Interface
      17. 3.4.17 Safety Connector
      18. 3.4.18 SPI Interfaces
      19. 3.4.19 I2C Interfaces
      20. 3.4.20 FSI Interface
  5. 4Known Issues and Modifications
    1. 4.1 Issue 1 - Embedded XDS110 Connection to AM64x Target in CCS
    2. 4.2 Issue 2 - MDIO Ethernet PHY Communications
    3. 4.3 Issue 3 - DC Barrel Jack Warning when Hot-Plugging
  6. 5References
  7. 6Revision History

3.4.19 I2C Interfaces

There are five I2C interfaces used in the GP EVM board.

  1. MAIN_I2C0: This interface is used by the software to identify the EVM and to control the power supply circuit. It is interfaced to presence detect latch to identify the daughter cards which are presently installed, Board ID memory device, board ID memories of the daughter cards and HSE connector. This I2C is also connected to a test header J5 for AM64x/AM243x processor slave operation. Pin outs of I2C test header is given in Table 3-28.
    Table 3-28 I2C Test Header (J5) Pin-out
    Pin No. Signal
    1 DGND
    2 SoC_I2C0_SDA
    3 SoC_I2C0_SCL
  2. MAIN_I2C1: This is interfaced to 16 bit GPIO expanders that is being used for all control signals and LED controls, 8bit LED Driver with part number TPIC2810, Current Monitors with part number INA226 to monitor current of VDD_CORE, VDDAR_CORE, SoC_DVDD3V3, SoC_DVDD1V8, VDDA_1V8, VDD_DDR4 , Temperature sensor with part number TMP100, Display Interface with part number OSD9616P0992-10, Test automation connector via voltage isolation. This I2C is also connected to a test header J4 for AM64x processor slave operation. Pin outs of I2C test header is given in Table 3-29.
    Table 3-29 I2C Test Header (J4) Pin-out
    Pin No. Signal
    1 SoC_I2C1_SCL
    2 SoC_I2C0_SDA
    3 DGND
    4 INA_ALERT
    5 NC
  3. MAIN_I2C3: This is connected to the expansion board connector from a mux. I2C3 is muxed with the MCAN signals. The default state of the mux is MCAN.
  4. MCU_I2C0: This is connected to the safety connector.
  5. MCU_I2C1: This is connected to the safety connector.

Figure 3-30 depicts the I2C tree.

GUID-7C042D8D-465D-4EAE-8FF2-0C0F44DDC941-low.jpg Figure 3-30 AM64x/AM243x I2C Interfaces and Address Assignment of Peripherals