SPRUIX0D
February 2021 – August 2021
Trademarks
1
Introduction
1.1
EVM Revisions and Assembly Variants
2
Important Usage Notes
2.1
Power-On Usage Note
3
System Description
3.1
Key Features
3.2
Functional Block Diagram
3.3
Power-On/Off Procedures
3.3.1
Power-On Procedure
3.3.2
Power-Off Procedure
3.4
Peripheral and Major Component Description
3.4.1
Clocking
3.4.1.1
Ethernet PHY Clock
3.4.1.2
AM64x/AM243x Clock
3.4.1.3
PCIe Clock
3.4.2
Reset
3.4.3
Power
3.4.3.1
Power Input
3.4.3.2
Reverse Polarity Protection
3.4.3.3
Current Monitoring
3.4.3.4
Power Supply
3.4.3.5
Power Sequencing
3.4.3.6
AM64x/AM243x Power
3.4.4
Configuration
3.4.4.1
Boot Modes
3.4.5
JTAG
3.4.6
Test Automation
3.4.7
UART Interfaces
3.4.8
Memory Interfaces
3.4.8.1
DDR4 Interface
3.4.8.2
MMC Interfaces
3.4.8.2.1
Micro SD Interface
3.4.8.2.2
eMMC Interface
3.4.8.3
OSPI Interface
3.4.8.4
SPI EEPROM Interface
3.4.8.5
Board ID EEPROM Interface
3.4.9
Ethernet Interface
3.4.9.1
DP83867 PHY Default Configuration
3.4.9.2
DP83869 PHY Default Configuration
3.4.9.3
Ethernet LED
3.4.10
Display Interface
3.4.11
USB 2.0 Interface
3.4.12
PCIe Interface
3.4.13
High Speed Expansion Interface
3.4.14
CAN Interface
3.4.15
Interrupt
3.4.16
ADC Interface
3.4.17
Safety Connector
3.4.18
SPI Interfaces
3.4.19
I2C Interfaces
3.4.20
FSI Interface
4
Known Issues and Modifications
4.1
Issue 1 - Embedded XDS110 Connection to AM64x Target in CCS
4.2
Issue 2 - MDIO Ethernet PHY Communications
4.3
Issue 3 - DC Barrel Jack Warning when Hot-Plugging
5
References
6
Revision History
5
References
AM64x Sitara™ Processors Data Manual
AM64x Processors Silicon Revision 1.0 Texas Instruments Families of Products Technical Reference Manual