SPRUIX0D February 2021 – August 2021
Three Ethernet PHYs terminated to RJ45 connectors with integrated magnetics is supported on the EVM.
The first PHY (connected to RJ45 connector J14) is interfaced to the CPSW_RGMII1 port of the SoC. The DP83867 PHY has been selected for this interface based on its ability to configure the Tx and Rx Delays. Since the CPSW_RGMII1_RX port is also multiplexed with PRG0 signals, a mux is needed to select the path from the SoC to this PHY (in CPSW mode) or to the HSE connector (PRG0 mode). The selection is done using a GPIO from the 24 bit IO expander.
The second PHY (connected to stacked RJ45 connector J21B) is interfaced to the PRG1_RGMII2 port of the SoC. This port is directly multiplexed with the CPSW_RGMII2 port. In order to select between CPSW and PRG operation, we need to multiplex the MDIO MDC signals from each controller to this PHY and the mux shall be controlled by a GPIO from IO expander. PRG1_RGMII2 is also internally multiplexed with PRG1_MII signals. The objective of the PHY used to connect this port is that the PHY should support both RGMII and MII modes, hence DP83869 (48 pin) PHY is selected.
The third PHY (connected to stacked RJ45 connector J21A ) is interfaced to the PRG1_RGMII1 port of the SoC. ICSSG ports support internal multiplexing of GPI, GPO, RGMII, MII etc. The objective of this PHY used to connect to this port is that it should support both RGMII and MII modes (without the use of CRS and COL signals as they are multiplexed with the CPSW_RGMII1 used for the first PHY). Hence the same DP83869 (48pin) PHY is used for this port as well.