SPRUIX0D February   2021  – August 2021

 

  1.   Trademarks
  2. 1Introduction
    1. 1.1 EVM Revisions and Assembly Variants
  3. 2Important Usage Notes
    1. 2.1 Power-On Usage Note
  4. 3System Description
    1. 3.1 Key Features
    2. 3.2 Functional Block Diagram
    3. 3.3 Power-On/Off Procedures
      1. 3.3.1 Power-On Procedure
      2. 3.3.2 Power-Off Procedure
    4. 3.4 Peripheral and Major Component Description
      1. 3.4.1  Clocking
        1. 3.4.1.1 Ethernet PHY Clock
        2. 3.4.1.2 AM64x/AM243x Clock
        3. 3.4.1.3 PCIe Clock
      2. 3.4.2  Reset
      3. 3.4.3  Power
        1. 3.4.3.1 Power Input
        2. 3.4.3.2 Reverse Polarity Protection
        3. 3.4.3.3 Current Monitoring
        4. 3.4.3.4 Power Supply
        5. 3.4.3.5 Power Sequencing
        6. 3.4.3.6 AM64x/AM243x Power
      4. 3.4.4  Configuration
        1. 3.4.4.1 Boot Modes
      5. 3.4.5  JTAG
      6. 3.4.6  Test Automation
      7. 3.4.7  UART Interfaces
      8. 3.4.8  Memory Interfaces
        1. 3.4.8.1 DDR4 Interface
        2. 3.4.8.2 MMC Interfaces
          1. 3.4.8.2.1 Micro SD Interface
          2. 3.4.8.2.2 eMMC Interface
        3. 3.4.8.3 OSPI Interface
        4. 3.4.8.4 SPI EEPROM Interface
        5. 3.4.8.5 Board ID EEPROM Interface
      9. 3.4.9  Ethernet Interface
        1. 3.4.9.1 DP83867 PHY Default Configuration
        2. 3.4.9.2 DP83869 PHY Default Configuration
        3. 3.4.9.3 Ethernet LED
      10. 3.4.10 Display Interface
      11. 3.4.11 USB 2.0 Interface
      12. 3.4.12 PCIe Interface
      13. 3.4.13 High Speed Expansion Interface
      14. 3.4.14 CAN Interface
      15. 3.4.15 Interrupt
      16. 3.4.16 ADC Interface
      17. 3.4.17 Safety Connector
      18. 3.4.18 SPI Interfaces
      19. 3.4.19 I2C Interfaces
      20. 3.4.20 FSI Interface
  5. 4Known Issues and Modifications
    1. 4.1 Issue 1 - Embedded XDS110 Connection to AM64x Target in CCS
    2. 4.2 Issue 2 - MDIO Ethernet PHY Communications
    3. 4.3 Issue 3 - DC Barrel Jack Warning when Hot-Plugging
  6. 5References
  7. 6Revision History
3.4.8.2.1 Micro SD Interface

The processor board provides an uSD card interface connected to MMC1 port of AM64x SoC. The uSD card interface supports UHS1 operation including operations at both 1.8V and 3.3V IO levels.. The AM64x SoC includes a circuit to generate the uSD voltage based on IO level negotiation with the uSD card. For high-speed cards, ROM code of the SoC attempts to find the fastest speed that the card and controller can support and can have a transition to 1.8V. The internal SDIO LDO output from the SoC is provided on the CAP_VDDSHV_SDLDO pin. CAP_VDDSHV_SDLDO is connected to both the IO voltage of SD signals and VDDSHV_MMC1 power pins of the SoC.

GUID-5D1A9DCB-9C5F-47E2-9F46-84CF82F779DE-low.png Figure 3-15 Micro SD Interface