SWCU191 February 2022 CC1311P3 , CC1311R3 , CC2651P3 , CC2651R3 , CC2651R3SIPA
In this scenario the user:
Figure 20-8 shows the scenario for synchronous counter start – ignore 0 stop events.
Table 20-11 lists the associated timing requirements for this scenario.
Description | Label | Requirement |
---|---|---|
Minimum high time | t_minH | 42 ns |
Minimum low time | t_minL | 126 ns |
Minimum delay | t_d | 21 ns |