SWCU191 February 2022 CC1311P3 , CC1311R3 , CC2651P3 , CC2651R3 , CC2651R3SIPA
Internal registers of the AES module are accessed by the slave interface. The AHB slave interface accepts 8-, 16-, and 32-bit transfers. However, the AES module accepts only 32-bit single access.
As each transfer is checked for multiple error conditions depending on the address, size and type of the transfer, these checks are performed on registered signals to improve timing on the input signals. Therefore, one wait cycle must be inserted for each transfer. If an ERROR response occurs, h_ready_out must be taken low one cycle after the address is received. This results in the following timing: