SWCU191 February 2022 CC1311P3 , CC1311R3 , CC2651P3 , CC2651R3 , CC2651R3SIPA
#CC26_MCU_SRAM_MEM_CC26_MCU_SRAM_MEM_MAP_SRAM_TABLE_1 lists the memory-mapped registers for the SRAM registers. All register offset addresses not listed in #CC26_MCU_SRAM_MEM_CC26_MCU_SRAM_MEM_MAP_SRAM_TABLE_1 should be considered as reserved locations and the register contents should not be modified.
Offset | Acronym | Register Name | Section |
---|---|---|---|
0h + formula | BANK0_y | 32k SRAM | #CC26_MCU_SRAM_MEM_CC26_MCU_SRAM_MEM_MAP_SRAM_CC26_MCU_SRAM_MEM_ALL_BANK0 |
Complex bit access types are encoded to fit into small table cells. #CC26_MCU_SRAM_MEM_CC26_MCU_SRAM_MEM_MAP_SRAM_LEGEND shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
Write Type | ||
W | W | Write |
Reset or Default Value | ||
-n | Value after reset or the default value | |
Register Array Variables | ||
i,j,k,l,m,n | When these variables are used in a register name, an offset, or an address, they refer to the value of a register array where the register is part of a group of repeating registers. The register groups form a hierarchical structure and the array is represented with a formula. | |
y | When this variable is used in a register name, an offset, or an address it refers to the value of a register array. |
BANK0_y is shown in #CC26_MCU_SRAM_MEM_CC26_MCU_SRAM_MEM_MAP_SRAM_CC26_MCU_SRAM_MEM_ALL_BANK0_FIGURE and described in #CC26_MCU_SRAM_MEM_CC26_MCU_SRAM_MEM_MAP_SRAM_CC26_MCU_SRAM_MEM_ALL_BANK0_TABLE.
Return to the Summary Table.
32k SRAM
Offset = 0h + (y * 4h); where y = 0h to 1FFFh
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA | |||||||||||||||||||||||||||||||
R/W-X | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | DATA | R/W | X | SRAM data |