SWCU191 February 2022 CC1311P3 , CC1311R3 , CC2651P3 , CC2651R3 , CC2651R3SIPA
The register configuration follows:
DATA_DELAY + (WORD_LEN × channel count) must be equal to or less than the number of BCLK periods per phase.
The channel count is determined by the MSB set in the I2S:AIFWMASK0 and I2S:AIFWMASK1 registers.