SWCU191 February 2022 CC1311P3 , CC1311R3 , CC2651P3 , CC2651R3 , CC2651R3SIPA
The CC13x1x3 and CC26x1x3 device platform provides 32 kB of low-leakage, on-chip SRAM with optional retention in all power modes. Retention can be configured per 16 kB block. Additionally, the 8 kB flash cache RAM can be reconfigured to operate as normal system RAM. Because read-modify-write (RMW) operations are very time consuming, Arm® has introduced bit-banding technology in the Arm® Cortex®-M4 processor. With a bit-band-enabled processor, certain regions in the memory map (SRAM and peripheral space) can use address aliases to access individual bits in a single, atomic operation.
Data can be transferred to and from the SRAM using the micro DMA (µDMA) controller.