SWCU191 February 2022 CC1311P3 , CC1311R3 , CC2651P3 , CC2651R3 , CC2651R3SIPA
The debug subsystem has only one slave DAP (CPU DAP). This debug port implements Serial Wire JTAG Debug Port (SWJ-DP) interface, which allows external access to an Advanced High-performance Bus Access Port (AHB-AP) interface for debug accesses in the CPU.
The SWJ-DP is a standard Arm CoreSight™ debug port that combines JTAG-DP and Serial Wire Debug Port (SW-DP). Even though the SW-DP interface is supported by SWJ-DP, the CC13x1x3 and CC26x1x3 device platform does not use this mode. The key reason is that SW-DP becomes redundant for the design in the presence of the 2-pin JTAG (1149.7) mode.