SWCU191 February 2022 CC1311P3 , CC1311R3 , CC2651P3 , CC2651R3 , CC2651R3SIPA
#CC26_DMA_PL230_R0P0_CC26_DMA_PL230_R0P0_MAP1_TABLE_1 lists the memory-mapped registers for the μDMA registers. All register offset addresses not listed in #CC26_DMA_PL230_R0P0_CC26_DMA_PL230_R0P0_MAP1_TABLE_1 should be considered as reserved locations and the register contents should not be modified.
Complex bit access types are encoded to fit into small table cells. #CC26_DMA_PL230_R0P0_CC26_DMA_PL230_R0P0_MAP1_LEGEND shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
Write Type | ||
W | W | Write |
Reset or Default Value | ||
-n | Value after reset or the default value |
STATUS is shown in #CC26_DMA_PL230_R0P0_CC26_DMA_PL230_R0P0_MAP1_CC26_DMA_PL230_R0P0_ALL_STATUS_FIGURE and described in #CC26_DMA_PL230_R0P0_CC26_DMA_PL230_R0P0_MAP1_CC26_DMA_PL230_R0P0_ALL_STATUS_TABLE.
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Status
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
TEST | RESERVED | ||||||
R-0h | R-0h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | TOTALCHANNELS | ||||||
R-0h | R-1Fh | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
STATE | RESERVED | MASTERENABLE | |||||
R-0h | R-0h | R-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-28 | TEST | R | 0h | 0x0: Controller does not include the integration test logic 0x1: Controller includes the integration test logic 0x2: Undefined ... 0xF: Undefined |
27-21 | RESERVED | R | 0h | Reserved |
20-16 | TOTALCHANNELS | R | 1Fh | Register value returns number of available μDMA channels minus one. For example a read out value of: 0x00: Show that the controller is configured to use 1 μDMA channel 0x01: Shows that the controller is configured to use 2 μDMA channels ... 0x1F: Shows that the controller is configured to use 32 μDMA channels (32-1=31=0x1F) |
15-8 | RESERVED | R | 0h | Reserved |
7-4 | STATE | R | 0h | Current state of the control state machine. State can be one of the following: 0x0: Idle 0x1: Reading channel controller data 0x2: Reading source data end pointer 0x3: Reading destination data end pointer 0x4: Reading source data 0x5: Writing destination data 0x6: Waiting for μDMA request to clear 0x7: Writing channel controller data 0x8: Stalled 0x9: Done 0xA: Peripheral scatter-gather transition 0xB: Undefined ... 0xF: Undefined. |
3-1 | RESERVED | R | 0h | Reserved |
0 | MASTERENABLE | R | 0h | Shows the enable status of the controller as configured by CFG.MASTERENABLE: 0: Controller is disabled 1: Controller is enabled |
CFG is shown in #CC26_DMA_PL230_R0P0_CC26_DMA_PL230_R0P0_MAP1_CC26_DMA_PL230_R0P0_ALL_CFG_FIGURE and described in #CC26_DMA_PL230_R0P0_CC26_DMA_PL230_R0P0_MAP1_CC26_DMA_PL230_R0P0_ALL_CFG_TABLE.
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Configuration
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRTOCTRL | RESERVED | MASTERENABLE | |||||
W-0h | R-0h | W-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-5 | PRTOCTRL | W | 0h | Sets the AHB-Lite bus protocol protection state by controlling the AHB signal HProt[3:1] as follows: Bit [7] Controls HProt[3] to indicate if a cacheable access is occurring. Bit [6] Controls HProt[2] to indicate if a bufferable access is occurring. Bit [5] Controls HProt[1] to indicate if a privileged access is occurring. When bit [n] = 1 then the corresponding HProt bit is high. When bit [n] = 0 then the corresponding HProt bit is low. This field controls HProt[3:1] signal for all transactions initiated by μDMA except two transactions below: - the read from the address indicated by source address pointer - the write to the address indicated by destination address pointer HProt[3:1] for these two exceptions can be controlled by dedicated fields in the channel configutation descriptor. |
4-1 | RESERVED | R | 0h | Reserved |
0 | MASTERENABLE | W | 0h | Enables the controller: 0: Disables the controller 1: Enables the controller |
CTRL is shown in #CC26_DMA_PL230_R0P0_CC26_DMA_PL230_R0P0_MAP1_CC26_DMA_PL230_R0P0_ALL_CTRL_FIGURE and described in #CC26_DMA_PL230_R0P0_CC26_DMA_PL230_R0P0_MAP1_CC26_DMA_PL230_R0P0_ALL_CTRL_TABLE.
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Channel Control Data Base Pointer
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BASEPTR | RESERVED | ||||||||||||||||||||||||||||||
R/W-0h | R-0h | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-10 | BASEPTR | R/W | 0h | This register point to the base address for the primary data structures of each μDMA channel. This is not stored in module, but in system memory, thus space must be allocated for this usage when μDMA is in usage |
9-0 | RESERVED | R | 0h | Reserved |
ALTCTRL is shown in #CC26_DMA_PL230_R0P0_CC26_DMA_PL230_R0P0_MAP1_CC26_DMA_PL230_R0P0_ALL_ALTCTRL_FIGURE and described in #CC26_DMA_PL230_R0P0_CC26_DMA_PL230_R0P0_MAP1_CC26_DMA_PL230_R0P0_ALL_ALTCTRL_TABLE.
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Channel Alternate Control Data Base Pointer
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BASEPTR | |||||||||||||||||||||||||||||||
R-200h | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | BASEPTR | R | 200h | This register shows the base address for the alternate data structures and is calculated by module, thus read only |
WAITONREQ is shown in #CC26_DMA_PL230_R0P0_CC26_DMA_PL230_R0P0_MAP1_CC26_DMA_PL230_R0P0_ALL_WAITONREQ_FIGURE and described in #CC26_DMA_PL230_R0P0_CC26_DMA_PL230_R0P0_MAP1_CC26_DMA_PL230_R0P0_ALL_WAITONREQ_TABLE.
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Channel Wait On Request Status
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CHNLSTATUS | |||||||||||||||||||||||||||||||
R-FFFF1EFFh | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | CHNLSTATUS | R | FFFF1EFFh | Channel wait on request status: Bit [Ch] = 0: Once μDMA receives a single or burst request on channel Ch, this channel may come out of active state even if request is still present. Bit [Ch] = 1: Once μDMA receives a single or burst request on channel Ch, it keeps channel Ch in active state until the requests are deasserted. This handshake is necessary for channels where the requester is in an asynchronous domain or can run at slower clock speed than μDMA |
SOFTREQ is shown in #CC26_DMA_PL230_R0P0_CC26_DMA_PL230_R0P0_MAP1_CC26_DMA_PL230_R0P0_ALL_SOFTREQ_FIGURE and described in #CC26_DMA_PL230_R0P0_CC26_DMA_PL230_R0P0_MAP1_CC26_DMA_PL230_R0P0_ALL_SOFTREQ_TABLE.
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Channel Software Request
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CHNLS | |||||||||||||||||||||||||||||||
W-0h | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | CHNLS | W | 0h | Set the appropriate bit to generate a software μDMA request on the corresponding μDMA channel Bit [Ch] = 0: Does not create a μDMA request for channel Ch Bit [Ch] = 1: Creates a μDMA request for channel Ch Writing to a bit where a μDMA channel is not implemented does not create a μDMA request for that channel |
SETBURST is shown in #CC26_DMA_PL230_R0P0_CC26_DMA_PL230_R0P0_MAP1_CC26_DMA_PL230_R0P0_ALL_SETBURST_FIGURE and described in #CC26_DMA_PL230_R0P0_CC26_DMA_PL230_R0P0_MAP1_CC26_DMA_PL230_R0P0_ALL_SETBURST_TABLE.
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Channel Set UseBurst
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CHNLS | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | CHNLS | R/W | 0h | Returns the useburst status, or disables individual channels from generating single μDMA requests. The value R is the arbitration rate and stored in the controller data structure. Read as: Bit [Ch] = 0: μDMA channel Ch responds to both burst and single requests on channel C. The controller performs 2R, or single, bus transfers. Bit [Ch] = 1: μDMA channel Ch does not respond to single transfer requests. The controller only responds to burst transfer requests and performs 2R transfers. Write as: Bit [Ch] = 0: No effect. Use the CLEARBURST.CHNLS to set bit [Ch] to 0. Bit [Ch] = 1: Disables single transfer requests on channel Ch. The controller performs 2R transfers for burst requests. Writing to a bit where a μDMA channel is not implemented has no effect |
CLEARBURST is shown in #CC26_DMA_PL230_R0P0_CC26_DMA_PL230_R0P0_MAP1_CC26_DMA_PL230_R0P0_ALL_CLEARBURST_FIGURE and described in #CC26_DMA_PL230_R0P0_CC26_DMA_PL230_R0P0_MAP1_CC26_DMA_PL230_R0P0_ALL_CLEARBURST_TABLE.
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Channel Clear UseBurst
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CHNLS | |||||||||||||||||||||||||||||||
W-0h | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | CHNLS | W | 0h | Set the appropriate bit to enable single transfer requests. Write as: Bit [Ch] = 0: No effect. Use the SETBURST.CHNLS to disable single transfer requests. Bit [Ch] = 1: Enables single transfer requests on channel Ch. Writing to a bit where a μDMA channel is not implemented has no effect. |
SETREQMASK is shown in #CC26_DMA_PL230_R0P0_CC26_DMA_PL230_R0P0_MAP1_CC26_DMA_PL230_R0P0_ALL_SETREQMASK_FIGURE and described in #CC26_DMA_PL230_R0P0_CC26_DMA_PL230_R0P0_MAP1_CC26_DMA_PL230_R0P0_ALL_SETREQMASK_TABLE.
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Channel Set Request Mask
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CHNLS | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | CHNLS | R/W | 0h | Returns the burst and single request mask status, or disables the corresponding channel from generating μDMA requests. Read as: Bit [Ch] = 0: External requests are enabled for channel Ch. Bit [Ch] = 1: External requests are disabled for channel Ch. Write as: Bit [Ch] = 0: No effect. Use the CLEARREQMASK.CHNLS to enable μDMA requests. Bit [Ch] = 1: Disables μDMA burst request channel [C] and μDMA single request channel [C] input from generating μDMA requests. Writing to a bit where a μDMA channel is not implemented has no effect |
CLEARREQMASK is shown in #CC26_DMA_PL230_R0P0_CC26_DMA_PL230_R0P0_MAP1_CC26_DMA_PL230_R0P0_ALL_CLEARREQMASK_FIGURE and described in #CC26_DMA_PL230_R0P0_CC26_DMA_PL230_R0P0_MAP1_CC26_DMA_PL230_R0P0_ALL_CLEARREQMASK_TABLE.
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Clear Channel Request Mask
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CHNLS | |||||||||||||||||||||||||||||||
W-0h | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | CHNLS | W | 0h | Set the appropriate bit to enable μDMA request for the channel. Write as: Bit [Ch] = 0: No effect. Use the SETREQMASK.CHNLS to disable channel C from generating requests. Bit [Ch] = 1: Enables channel [C] to generate μDMA requests. Writing to a bit where a μDMA channel is not implemented has no effect. |
SETCHANNELEN is shown in #CC26_DMA_PL230_R0P0_CC26_DMA_PL230_R0P0_MAP1_CC26_DMA_PL230_R0P0_ALL_SETCHANNELEN_FIGURE and described in #CC26_DMA_PL230_R0P0_CC26_DMA_PL230_R0P0_MAP1_CC26_DMA_PL230_R0P0_ALL_SETCHANNELEN_TABLE.
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Set Channel Enable
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CHNLS | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | CHNLS | R/W | 0h | Returns the enable status of the channels, or enables the corresponding channels. Read as: Bit [Ch] = 0: Channel Ch is disabled. Bit [Ch] = 1: Channel Ch is enabled. Write as: Bit [Ch] = 0: No effect. Use the CLEARCHANNELEN.CHNLS to disable a channel Bit [Ch] = 1: Enables channel Ch Writing to a bit where a μDMA channel is not implemented has no effect |
CLEARCHANNELEN is shown in #CC26_DMA_PL230_R0P0_CC26_DMA_PL230_R0P0_MAP1_CC26_DMA_PL230_R0P0_ALL_CLEARCHANNELEN_FIGURE and described in #CC26_DMA_PL230_R0P0_CC26_DMA_PL230_R0P0_MAP1_CC26_DMA_PL230_R0P0_ALL_CLEARCHANNELEN_TABLE.
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Clear Channel Enable
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CHNLS | |||||||||||||||||||||||||||||||
W-0h | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | CHNLS | W | 0h | Set the appropriate bit to disable the corresponding μDMA channel. Write as: Bit [Ch] = 0: No effect. Use the SETCHANNELEN.CHNLS to enable μDMA channels. Bit [Ch] = 1: Disables channel Ch Writing to a bit where a μDMA channel is not implemented has no effect |
SETCHNLPRIALT is shown in #CC26_DMA_PL230_R0P0_CC26_DMA_PL230_R0P0_MAP1_CC26_DMA_PL230_R0P0_ALL_SETCHNLPRIALT_FIGURE and described in #CC26_DMA_PL230_R0P0_CC26_DMA_PL230_R0P0_MAP1_CC26_DMA_PL230_R0P0_ALL_SETCHNLPRIALT_TABLE.
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Channel Set Primary-Alternate
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CHNLS | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | CHNLS | R/W | 0h | Returns the channel control data structure status, or selects the alternate data structure for the corresponding μDMA channel. Read as: Bit [Ch] = 0: μDMA channel Ch is using the primary data structure. Bit [Ch] = 1: μDMA channel Ch is using the alternate data structure. Write as: Bit [Ch] = 0: No effect. Use the CLEARCHNLPRIALT.CHNLS to disable a channel Bit [Ch] = 1: Selects the alternate data structure for channel Ch Writing to a bit where a μDMA channel is not implemented has no effect |
CLEARCHNLPRIALT is shown in #CC26_DMA_PL230_R0P0_CC26_DMA_PL230_R0P0_MAP1_CC26_DMA_PL230_R0P0_ALL_CLEARCHNLPRIALT_FIGURE and described in #CC26_DMA_PL230_R0P0_CC26_DMA_PL230_R0P0_MAP1_CC26_DMA_PL230_R0P0_ALL_CLEARCHNLPRIALT_TABLE.
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Channel Clear Primary-Alternate
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CHNLS | |||||||||||||||||||||||||||||||
W-0h | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | CHNLS | W | 0h | Clears the appropriate bit to select the primary data structure for the corresponding μDMA channel. Write as: Bit [Ch] = 0: No effect. Use the SETCHNLPRIALT.CHNLS to select the alternate data structure. Bit [Ch] = 1: Selects the primary data structure for channel Ch. Writing to a bit where a μDMA channel is not implemented has no effect |
SETCHNLPRIORITY is shown in #CC26_DMA_PL230_R0P0_CC26_DMA_PL230_R0P0_MAP1_CC26_DMA_PL230_R0P0_ALL_SETCHNLPRIORITY_FIGURE and described in #CC26_DMA_PL230_R0P0_CC26_DMA_PL230_R0P0_MAP1_CC26_DMA_PL230_R0P0_ALL_SETCHNLPRIORITY_TABLE.
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Set Channel Priority
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CHNLS | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | CHNLS | R/W | 0h | Returns the channel priority mask status, or sets the channel priority to high. Read as: Bit [Ch] = 0: μDMA channel Ch is using the default priority level. Bit [Ch] = 1: μDMA channel Ch is using a high priority level. Write as: Bit [Ch] = 0: No effect. Use the CLEARCHNLPRIORITY.CHNLS to set channel Ch to the default priority level. Bit [Ch] = 1: Channel Ch uses the high priority level. Writing to a bit where a μDMA channel is not implemented has no effect |
CLEARCHNLPRIORITY is shown in #CC26_DMA_PL230_R0P0_CC26_DMA_PL230_R0P0_MAP1_CC26_DMA_PL230_R0P0_ALL_CLEARCHNLPRIORITY_FIGURE and described in #CC26_DMA_PL230_R0P0_CC26_DMA_PL230_R0P0_MAP1_CC26_DMA_PL230_R0P0_ALL_CLEARCHNLPRIORITY_TABLE.
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Clear Channel Priority
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CHNLS | |||||||||||||||||||||||||||||||
W-0h | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | CHNLS | W | 0h | Clear the appropriate bit to select the default priority level for the specified μDMA channel. Write as: Bit [Ch] = 0: No effect. Use the SETCHNLPRIORITY.CHNLS to set channel Ch to the high priority level. Bit [Ch] = 1: Channel Ch uses the default priority level. Writing to a bit where a μDMA channel is not implemented has no effect |
ERROR is shown in #CC26_DMA_PL230_R0P0_CC26_DMA_PL230_R0P0_MAP1_CC26_DMA_PL230_R0P0_ALL_ERROR_FIGURE and described in #CC26_DMA_PL230_R0P0_CC26_DMA_PL230_R0P0_MAP1_CC26_DMA_PL230_R0P0_ALL_ERROR_TABLE.
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Error Status and Clear
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | STATUS | ||||||
R-0h | R/W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | Reserved |
0 | STATUS | R/W | 0h | Returns the status of bus error flag in μDMA, or clears this bit Read as: 0: No bus error detected 1: Bus error detected Write as: 0: No effect, status of bus error flag is unchanged. 1: Clears the bus error flag. |
REQDONE is shown in #CC26_DMA_PL230_R0P0_CC26_DMA_PL230_R0P0_MAP1_CC26_DMA_PL230_R0P0_ALL_REQDONE_FIGURE and described in #CC26_DMA_PL230_R0P0_CC26_DMA_PL230_R0P0_MAP1_CC26_DMA_PL230_R0P0_ALL_REQDONE_TABLE.
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Channel Request Done
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CHNLS | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | CHNLS | R/W | 0h | Reflects the μDMA done status for the given channel, channel [Ch]. It's a sticky done bit. Unless cleared by writing a 1, it holds the value of 1. Read as: Bit [Ch] = 0: Request has not completed for channel Ch Bit [Ch] = 1: Request has completed for the channel Ch Writing a 1 to individual bits would clear the corresponding bit. Write as: Bit [Ch] = 0: No effect. Bit [Ch] = 1: The corresponding [Ch] bit is cleared and is set to 0 |
DONEMASK is shown in #CC26_DMA_PL230_R0P0_CC26_DMA_PL230_R0P0_MAP1_CC26_DMA_PL230_R0P0_ALL_DONEMASK_FIGURE and described in #CC26_DMA_PL230_R0P0_CC26_DMA_PL230_R0P0_MAP1_CC26_DMA_PL230_R0P0_ALL_DONEMASK_TABLE.
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Channel Request Done Mask
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CHNLS | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | CHNLS | R/W | 0h | Controls the propagation of the μDMA done and active state to the assigned peripheral. Specifically used for software channels. Read as: Bit [Ch] = 0: μDMA done and active state for channel Ch is not blocked from reaching to the peripherals. Note that the μDMA done state for channel [Ch] is blocked from contributing to generation of combined μDMA done signal Bit [Ch] = 1: μDMA done and active state for channel Ch is blocked from reaching to the peripherals. Note that the μDMA done state for channel [Ch] is not blocked from contributing to generation of combined μDMA done signal Write as: Bit [Ch] = 0: Allows μDMA done and active stat to propagate to the peripherals. Note that this disables μDMA done state for channel [Ch] from contributing to generation of combined μDMA done signal Bit [Ch] = 1: Blocks μDMA done and active state to propagate to the peripherals. Note that this enables μDMA done for channel [Ch] to contribute to generation of combined μDMA done signal. |