SWCU191 February 2022 CC1311P3 , CC1311R3 , CC2651P3 , CC2651R3 , CC2651R3SIPA
Table 13-1 lists the memory map details. See Section 13.9.1 for the descriptions.
Physical Address | Register Name | Type | Reset Value | Remark |
---|---|---|---|---|
DMA Controller Registers | ||||
0x4002 4000 | DMACH0CTL | R/W | 0x0000 0000 | Channel 0 control register |
0x4002 4004 | DMACH0EXTADDR | R/W | 0x0000 0000 | Channel 0 external address |
0x4002 400C | DMACH0LEN | R/W | 0x0000 0000 | Channel 0 DMA length |
0x4002 4018 | DMASTAT | R | 0x0000 0000 | DMAC status |
0x4002 401C | DMASWRESET | W | 0x0000 0000 | DMAC software reset |
0x4002 4020 | DMACH1CTL | R/W | 0x0000 0000 | Channel 1 control register |
0x4002 4024 | DMACH1EXTADDR | R/W | 0x0000 0000 | Channel 1 external address |
0x4002 402C | DMACH1LEN | R/W | 0x0000 0000 | Channel 1 DMA length |
0x4002 4078 | DMABUSCFG | R/W | 0x0000 6000 | Master runtime parameters |
0x4002 407C | DMAPORTERR | R | 0x0000 0000 | Port error raw status register |
0x4002 40F8 | DMAHWOPT | R | 0x0000 0202 | DMAC options register |
0x4002 40FC | DMAHWVER | R | 0x0101 2ED1 | DMAC version register |
Key-Storage Registers | ||||
0x4002 4400 | KEYWRITEAREA | R/W | 0x0000 0000 | Writer area register |
0x4002 4404 | KEYWRITTENAREA | R/W | 0x0000 0000 | Written area register |
0x4002 4408 | KEYSIZE | R/W | 0x0000 0001 | Key size register |
0x4002 440C | KEYREADAREA | R/W | 0x0000 0008 | Read area register |
AES Engine Registers | ||||
0x4002 4500 to 0x4002 450C | AESKEY2_0 to AESKEY2_3 | W | 0x0000 0000 | Clear/wipe AESKEY2__0 to AESKEY2__3 register |
0x4002 4510 to 0x4002 451C | AESKEY3_0 to AESKEY3_3 | W | 0x0000 0000 | Clear/wipe AESKEY3__0 to AESKEY3__3 register |
0x4002 4540 to 0x4002 454C | AESIV_0 to AESIV_3 | R/W | 0x0000 0000 | AES IV (LSW) |
0x4002 4550 | AESCTL | R/W | 0x8000 0000 | I/O and control mode |
0x4002 4554 | AESDATALEN0 | W | 0x0000 0000 | Crypto data length (LSW) |
0x4002 4558 | AESDATALEN1 | W | 0x0000 0000 | Crypto data length (MSW) |
0x4002 455C | AESAUTHLEN | W | 0x0000 0000 | AAD data length |
0x4002 4560 | AESDATAOUT0 | R | 0x0000 0000 | Data output (LSW) |
0x4002 4560 | AESDATAIN0 | W | 0x0000 0000 | Data input (LSW) |
0x4002 4564 | AESDATAOUT1 | R | 0x0000 0000 | Data output |
0x4002 4564 | AESDATAIN1 | W | 0x0000 0000 | Data input |
0x4002 4568 | AESDATAOUT2 | R | 0x0000 0000 | Data output |
0x4002 4568 | AESDATAIN2 | W | 0x0000 0000 | Data input |
0x4002 456C | AESDATAOUT3 | R | 0x0000 0000 | Data output (MSW) |
0x4002 456C | AESDATAIN3 | W | 0x0000 0000 | Data input (MSW) |
0x4002 4570 to 0x4002 4057C | AESTAGOUT_0 to AESTAGOUT_3 | W | 0x0000 0000 | Tag output (LSW) |
Master-Control Registers | ||||
0x4002 4700 | ALGSEL | R/W | 0x0000 0000 | Algorithm selection |
0x4002 4704 | DMAPROTCTL | R/W | 0x0000 0000 | Enable privileged access on master |
0x4002 4740 | SWRESET | W | 0x0000 0000 | Master control software reset |
0x4002 4780 | IRQTYPE | R/W | 0x0000 0000 | Interrupt configuration register |
0x4002 4784 | IRQEN | R/W | 0x0000 0000 | Interrupt enabling register |
0x4002 4788 | IRQCLR | W | 0x0000 0000 | Interrupt clear register |
0x4002 478C | IRQSET | W | 0x0000 0000 | Interrupt set register |
0x4002 4790 | IRQSTAT | R | 0x0000 0000 | Interrupt status register |
0x4002 47F8 | HWOPT | R | 0x0101 01F7 | Type and options register |
0x4002 47FC | HWVER | R | 0x9200 8778 | Version register |